Wavelength division multiplexed loop buffer memory based optical packet switch

Abstract

Photonic all-optical switching is widely considered as one of the technique to utilize the enormous optical bandwidth. Optical packet switching provides high speed, data rate transparency, data format transparency, efficient use of bandwidth and flexibility. To resolve the conflict during contention, packets are needed to be buffered. Due to the lack of optical RAM, fiber delay lines (FDLs) are the most suited option to buffer the packets. This paper proposes new optical packet switch architecture alongwith feedback shared buffer utilizing the advantage of WDM loop buffer memory. The loop buffer module used in this switch architecture is a new approach towards WDM buffering of packets. The mathematical modeling is done to validate the results obtained from simulation.

AWG and EDFA based optical packet switch using feedback shared loop buffer memory

“…We have assumed that the controlling is done electronically, which tunes various components of the loop buffer as well as controls the whole switch (Fow-Sen Choa et al 2005;Singh et al 2007). The tuning speed of TWCs and the switching speed of space switch do not put any constraint on the switching operation.…”

“…In this paper, we are proposing a modification in the optical packet switch architecture (Singh et al 2007), which uses multiple loop buffer modules in the feedback sharing configuration. In Singh et al (2007), WDM based fiber delay lines are used to store the contending packets and a space switch is used to direct them appropriately.…”

“…In Singh et al (2007), WDM based fiber delay lines are used to store the contending packets and a space switch is used to direct them appropriately. The main disadvantage of the architecture is that the loss in signal power is very high, and it reduces the number of maximum allowed circulations by the data in loop buffer modules.…”

“…This will provide a relaxation in the circulation limit, which in turn results in the better packet loss probability and the average delay by effectively utilizing the available buffer capacity. Hence, this paper can be assumed as an extended and improved version of Singh et al (2007).…”

Performance Evaluation of Buffer under Load Balancing In High Speed Network

“…No sooner did the packet reaches the egress node (edge router from which packet exit the core network), then the collected packet can be isolated optically and made to go onto the client network. This kind of networking design is alluded as aggregate core transport networks [7][8][9]. The rest of the paper is organized as follows: section II of the paper describe buffering and deflection routing, section III of the paper gives proposed work, simulation results are presented in section IV of the paper, and finally section V of the paper concludes the work.…”