WCET-Aware Dynamic D-cache Locking for A Single Task

Zheng, Wenguang

doi:10.1145/2670529.2754965

Cited by 10 publications

(6 citation statements)

References 31 publications

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“…To minimize the performance degradation, the approach loads the cache with the data likely to be accessed. Zheng and Wu [2015] propose two D-cache locking approaches that aim at minimizing the WCET of a task. The first approach formulates the problem as a global ILP problem that simultaneously selects a near-optimal set of variables as the locked cache contents and allocates them to the D-cache.…”

Section: Related Workmentioning

confidence: 99%

WCET-Aware Dynamic I-Cache Locking for a Single Task

Zheng

Yang

2017

ACM Trans. Archit. Code Optim.

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Caches are widely used in embedded systems to bridge the increasing speed gap between processors and off-chip memory. However, caches make it significantly harder to compute the worst-case execution time (WCET) of a task. To alleviate this problem, cache locking has been proposed. We investigate the WCETaware I-cache locking problem and propose a novel dynamic I-cache locking heuristic approach for reducing the WCET of a task. For a nonnested loop, our approach aims at selecting a minimum set of memory blocks of the loop as locked cache contents by using the min-cut algorithm. For a loop nest, our approach not only aims at selecting a minimum set of memory blocks of the loop nest as locked cache contents but also finds a good loading point for each selected memory block. We propose two algorithms for finding a good loading point for each selected memory block, a polynomial-time heuristic algorithm and an integer linear programming (ILP)-based algorithm, further reducing the WCET of each loop nest. We have implemented our approach and compared it to two state-of-the-art I-cache locking approaches by using a set of benchmarks from the MRTC benchmark suite. The experimental results show that the polynomial-time heuristic algorithm for finding a good loading point for each selected memory block performs almost equally as well as the ILP-based algorithm. Compared to the partial locking approach proposed in Ding et al. [2012], our approach using the heuristic algorithm achieves the average improvements of 33%, 15%, 9%, 3%, 8%, and 11% for the 256B, 512B, 1KB, 4KB, 8KB, and 16KB caches, respectively. Compared to the dynamic locking approach proposed in Puaut [2006], it achieves the average improvements of 9%,

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Section: Related Workmentioning

confidence: 99%

WCET-Aware Dynamic I-Cache Locking for a Single Task

Zheng

Yang

2017

ACM Trans. Archit. Code Optim.

Self Cite

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“…Alternatively to conventional caches, lockable data caches could be used. A locked data cache is much easier to analyze, and its WCET-aware configuration can be included in the WCET analysis method [30], [34]. Still, the dynamism of data accesses severely restrict the effectiveness of locked data caches.…”

Section: Related Workmentioning

confidence: 99%

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

et al. 2020

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Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this paper, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%.

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“…Cache locking allows an application to load certain data into cache and prevents it from being evicted. Several static and dynamic cache locking schemes [18,81,65,7,75,87] have been proposed to improve timing predictability of tasks. While cache locking provides fine grained control over task data, it leads to poor utilization when data does not fit in the cache [81].…”

Section: Related Workmentioning

confidence: 99%

“…The problem of selecting critical data is similar to selecting/allocating optimal data for cache locking and scratch pad memory. A number of approaches have been proposed to identify the optimal set of variables as locked contents and map the selected data to cache memory [53,81,87,83]. Such methods could be leveraged to help automate the process of selecting what data to make critical.…”

Section: Application-level Usage Model Of Lc Cachementioning

confidence: 99%

“…Hence, to e ciently utilize the cache and improve WCET the choice of critical data is very important for tasks with large memory footprint. Existing static program analysis based techniques [53,81,87,83] for optimally selecting data for cache locking and scratch pad memory can be leveraged to identify and tag critical data o↵-line. Our LC cache design also provides the flexibility to change the critical address range and cache policy during run-time, which could be used as a mechanism to better utilize cache by adapting to changing operating conditions.…”

Section: Other Considerationsmentioning

confidence: 99%

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Hardware architecture support for mixed criticality and real-time systems

Govindaiah¹,

Kumar²

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WCET-Aware Dynamic D-cache Locking for A Single Task

Cited by 10 publications

References 31 publications

WCET-Aware Dynamic I-Cache Locking for a Single Task

WCET-Aware Dynamic I-Cache Locking for a Single Task

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

Hardware architecture support for mixed criticality and real-time systems

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