Wearout-aware compiler-directed register assignment for embedded systems

Ahmed, Fahad; Sabry, Mohamed M.; Atienza, David; Milor, Linda

doi:10.1109/isqed.2012.6187471

Cited by 6 publications

(6 citation statements)

References 25 publications

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“…This approach also requires intrusive architectural supports and pipeline modification. Wearout-aware compiler-directed register assignment techniques have been proposed in Ahmed et al [2012] that attempt to distribute the stress-induced wearout throughout the register file. Another aging-aware assignment of registers has been proposed to balance the duty cycle ratio of the internal bits in a register file [Wang et al 2012].…”

Section: Related Workmentioning

confidence: 99%

Aging-Aware Compilation for GP-GPUs

Lotfi

Rahimi

Benini

et al. 2015

ACM Trans. Archit. Code Optim.

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General-purpose graphic processing units (GP-GPUs) offer high computational throughput using thousands of integrated processing elements (PEs). These PEs are stressed during workload execution, and negative bias temperature instability (NBTI) adversely affects their reliability by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across the PEs: some are affected more-hence less reliable-than others. This variation causes significant reduction in the lifetime of GP-GPU parts. In this article, we address the problem of "wear leveling" across processing units to mitigate lifetime uncertainty in GP-GPUs. We propose innovations in the static compiled code that can improve healing in PEs and stream cores (SCs) based on their degradation status. PE healing is a fine-grained very long instruction word (VLIW) slot assignment scheme that balances the stress of instructions across the PEs within an SC. SC healing is a coarse-grained workload allocation scheme that distributes workload across SCs in GP-GPUs. Both schemes share a common property: they adaptively shift workload from less reliable units to more reliable units, either spatially or temporally. These software schemes are based on online calibration with NBTI monitoring that equalizes the expected lifetime of PEs and SCs by regenerating adaptive compiled codes to respond to the specific health state of the GP-GPUs. We evaluate the effectiveness of the proposed schemes for various OpenCL kernels from the AMD APP SDK on Evergreen and Southern Island GPU architectures. The aging-aware healthy kernels generated by the PE (or SC) healing scheme reduce NBTIinduced voltage threshold shift by 30% (77% in the case of SCs), with no (moderate) performance penalty compared to the naive kernels.

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Section: Related Workmentioning

confidence: 99%

Aging-Aware Compilation for GP-GPUs

Lotfi

Rahimi

Benini

et al. 2015

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…This approach also requires architectural supports and pipeline modification. Wearout-aware compiler-directed register assignment techniques have been proposed in [22] that attempt to distribute the stress-induced wearout throughout the register file. Another aging-aware assignment of registers has been proposed to balance the duty cycle ratio of the internal bits in register files [23].…”

Section: Related Workmentioning

confidence: 99%

“…Another aging-aware assignment of registers has been proposed to balance the duty cycle ratio of the internal bits in register files [23]. Even though [22], [23] do not impose architectural overheads and modification, their compiler strategies are limited to the utilization of the register file. NBTI-aware power-gating [14] exploits the sleep state where a circuit is intrinsically immune to aging.…”

Section: Related Workmentioning

confidence: 99%

Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Rahimi

Benini

Gupta

2013

Proceedings of the 50th Annual Design Automation Conference

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Negative bias temperature instability (NBTI) adversely affects the reliability of a processor by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across functional units and instructions: some are affected more (hence less reliable) than others. This paper proposes a NBTI-aware compiler-directed very long instruction word (VLIW) assignment scheme that uniformly distributes the stress of instructions with the aim of minimizing aging of GPGPU architecture without any performance penalty. The proposed solution is an entirely software technique based on static workload characterization and online execution with NBTI monitoring that equalizes the expected lifetime of each processing element by regenerating aging-aware healthy kernels that respond to the specific health state of GPGPU. We demonstrate our approach on AMD Evergreen architecture where iso-throughput executions of the healthy kernels reduce NBTI-induced voltage threshold shift up to 49% (11%) compared to naïve kernel executions, with (without) architectural support for power-gating. The kernel adaption flow takes average of 13 millisecond on a typical host machine thus making it suitable for practical implementation.

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“…These measures are intrusive and fairly complicated: the complement mode is applied to the whole data path, control path, and storage hierarchy. Wearout-aware compiler-directed register assignment techniques are proposed in [13] to distribute the stress-induced wearout throughout the RF. Even though [13] does not impose architectural overheads and modification, its compilerbased approach is only limited to single-threaded applications.…”

Section: Related Workmentioning

confidence: 99%

“…Wearout-aware compiler-directed register assignment techniques are proposed in [13] to distribute the stress-induced wearout throughout the RF. Even though [13] does not impose architectural overheads and modification, its compilerbased approach is only limited to single-threaded applications. Another aging-aware assignment of RF is also proposed to balance the duty cycle ratio of the internal bits in RF [14]; however, with balanced signal probabilities, there is still an inevitable static noise margin degradation [35], [36].…”

Section: Related Workmentioning

confidence: 99%

ARGO: Aging-aware GPGPU register file allocation

Namaki-Shoushtari¹,

Rahimi²,

Dutt³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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State-of-the-art general-purpose graphic processing units (GPGPUs) implemented in nanoscale CMOS technologies offer very high computational throughput for highly-parallel applications using hundreds of integrated on-chip resources. These resources are stressed during application execution, subjecting them to degradation mechanisms such as negative bias temperature instability (NBTI) that adversely affect their reliability. To support highly parallel execution, GPGPUs contain large register files (RFs) that are among the most highly stressed GPGPU components; however we observe heavy underutilization of RFs (on average only 46%) for typical general-purpose kernels. We present ARGO, an Aging-awaRe GPGPU RF allOcator that opportunistically exploits this RF underutilization by distributing the stress throughout RF. ARGO achieves proper leveling of RF banks through deliberated power-gating of stressful banks. We demonstrate our technique on the AMD Evergreen GPGPU architecture and show that ARGO improves the NBTI-induced threshold voltage degradation by up to 43% (on average 27%), that yields improving RFs static noise margin up to 46% (on average 30%). Furthermore, we estimate a simultaneous reduction in leakage power of 54% by providing sleep states for unused banks.

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Wearout-aware compiler-directed register assignment for embedded systems

Cited by 6 publications

References 25 publications

Aging-Aware Compilation for GP-GPUs

Aging-Aware Compilation for GP-GPUs

Aging-aware compiler-directed VLIW assignment for GPGPU architectures

ARGO: Aging-aware GPGPU register file allocation

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