Westmere: A family of 32nm IA processors

Kurd, Nasser; Bhamidipati, Subramani; Mozak, Christopher; Miller, Jeffrey L.; Wilson, Timothy M.; Nemani, Mahadev; Chowdhury, Muntaquim

doi:10.1109/isscc.2010.5434033

Cited by 63 publications

(49 citation statements)

References 2 publications

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“…This configuration is representative of modern high-performance servers [31,53]. The system supports per-core DVFS and sleep states modeled after Haswell [5,14].…”

Section: Experimental Methodologymentioning

confidence: 99%

Rubik

Kasture

Bartolini

Beckmann

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

117

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Latency-critical workloads (e.g., web search), common in datacenters, require stable tail (e.g., 95th percentile) latencies of a few milliseconds. Servers running these workloads are kept lightly loaded to meet these stringent latency targets. This low utilization wastes billions of dollars in energy and equipment annually.Applying dynamic power management to latency-critical workloads is challenging. The fundamental issue is coping with their inherent short-term variability: requests arrive at unpredictable times and have variable lengths. Without knowledge of the future, prior techniques either adapt slowly and conservatively or rely on application-specific heuristics to maintain tail latency.We propose Rubik, a fine-grain DVFS scheme for latency-critical workloads. Rubik copes with variability through a novel, general, and efficient statistical performance model. This model allows Rubik to adjust frequencies at sub-millisecond granularity to save power while meeting the target tail latency. Rubik saves up to 66% of core power, widely outperforms prior techniques, and requires no application-specific tuning.Beyond saving core power, Rubik robustly adapts to sudden changes in load and system performance. We use this capability to design RubikColoc, a colocation scheme that uses Rubik to allow batch and latencycritical work to share hardware resources more aggressively than prior techniques. RubikColoc reduces datacenter power by up to 31% while using 41% fewer servers than a datacenter that segregates latency-critical and batch work, and achieves 100% core utilization.

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“…This configuration is representative of modern high-performance servers [31,53]. The system supports per-core DVFS and sleep states modeled after Haswell [5,14].…”

Section: Experimental Methodologymentioning

confidence: 99%

Rubik

Kasture

Bartolini

Beckmann

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

117

View full text Add to dashboard Cite

show abstract

“…For the characterization experiments, we pin the application to one core, and simulate a 2 MB LLC except when noted (in line with the per-core LLC capacity of current CMPs [27]). All applications run a single server worker thread, although some applications have additional threads (e.g., shore-mt uses log writer threads to reduce I/O stalls).…”

Section: Methodsmentioning

confidence: 99%

Ubik

Kasture

Sánchez

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

115

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Chip-multiprocessors (CMPs) must often execute workload mixes with different performance requirements. On one hand, user-facing, latency-critical applications (e.g., web search) need low tail (i.e., worst-case) latencies, often in the millisecond range, and have inherently low utilization. On the other hand, compute-intensive batch applications (e.g., MapReduce) only need high long-term average performance. In current CMPs, latency-critical and batch applications cannot run concurrently due to interference on shared resources. Unfortunately, prior work on quality of service (QoS) in CMPs has focused on guaranteeing average performance, not tail latency.In this work, we analyze several latency-critical workloads, and show that guaranteeing average performance is insufficient to maintain low tail latency, because microarchitectural resources with state, such as caches or cores, exert inertia on instantaneous workload performance. Last-level caches impart the highest inertia, as workloads take tens of milliseconds to warm them up. When left unmanaged, or when managed with conventional QoS frameworks, shared last-level caches degrade tail latency significantly. Instead, we propose Ubik, a dynamic partitioning technique that predicts and exploits the transient behavior of latency-critical workloads to maintain their tail latency while maximizing the cache space available to batch applications. Using extensive simulations, we show that, while conventional QoS frameworks degrade tail latency by up to 2.3×, Ubik simultaneously maintains the tail latency of latency-critical workloads and significantly improves the performance of batch applications.

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“…2(b)), comprised of a critical path netlist with 12 transistors exhibiting local mismatch variation. 1 Failure is evaluated from a transient SPICE simulation, checking for a polarity of sense amplifier differential output that is consistent with the bitcell data.…”

Section: Spherical Importance Sampling Cost Analysismentioning

confidence: 99%

“…Embedded SRAM is a vital component of digital integrated circuits and often constitutes a dominant portion of chip area [1]. Therefore, the specifications of embedded SRAM have significant implications on the overall chip cost, power, performance, and yield.…”

Section: Introductionmentioning

confidence: 99%

Technique for Efficient Evaluation of SRAM Timing Failure

Qazi

Tikekar

Dolecek

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-This paper presents a technique to evaluate the timing variation of SRAM. Specifically, a method called loop flattening that reduces the evaluation of the timing statistics in the complex, highly structured circuit to that of a single chain of component circuits is justified. To then very quickly evaluate the timing delay of a single chain, a statistical method based on Importance Sampling augmented with targeted, high-dimensional, spherical sampling can be employed. The overall methodology has shown 650X or greater speed-up over the nominal Monte Carlo approach with 10.5% accuracy in probability. Examples based on both the large-signal and small-signal SRAM read path are discussed and a detailed comparison with state of the art accelerated statistical simulation techniques is given.

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Westmere: A family of 32nm IA processors

Cited by 63 publications

References 2 publications

Rubik

Rubik

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Technique for Efficient Evaluation of SRAM Timing Failure

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