When Channel Coding Hits the Implementation Wall

Abstract

The continuous demands for higher throughput, higher spectral efficiency, lower latencies, lower power and large scalability in communication systems impose large challenges on the baseband signal processing. In the future, throughput requirements far beyond 100 Gbit/s are expected, which is much higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone will not provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. The focus of this paper lies on channel coding, which is a major source of complexity in digital baseband processing. We will highlight implementation challenges for the most advanced channel coding techniques, i.e. Turbo codes, Low Density Parity Check (LDPC) codes and Polar codes and present decoder architectures for all three code classes that are designed for highest throughput.

Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs

“…For higher radix-orders, the Local-SOVA algorithm can be considered [23]. Since the MAP algorithm is compute dominated, we can give estimations on the silicon area of the decoder architectures on the basis of the total area occupied by the computational units [24]. These estimations do not include the area of the memories, since they are highly dependent on the available memory cuts which would result in a distortion of the comparison.…”

Scoring the Terabit/s Goal:Broadband Connectivity in 6G

“…Trade-offs must be made between parallelization, pipelining, iterations, and unrolling, linking with the code design and decoder architecture. Future performance and efficiency improvements could come from CMOS scaling, but the picture is quite complex [241]. Indeed, trade-offs must be made to cope with issues such as power density/dark silicon, interconnect delays, variability, and reliability.…”

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

“…The inner decoder at time t is fed by three sequences: the LLRs of the inner parity bits, the LLRs of the sequence defined in (2), and the a-priori LLRs. The inner decoder then produces the extrinsic LLRs and sends them back to the connected outer decoders.…”

“…Support for extreme data rates in wireless systems beyond 5G (B5G) is essential for many new applications, such as data kiosks, high capacity wireless backhauls, and wireless virtual and augmented reality [1]. These demanding throughput requirements directly translate to the digital baseband signal processing where channel coding is a main contributor of computational complexity [2] and is subject to major restrictions in terms of silicon area. Achieving Tbps throughputs with FEC schemes that rely on soft decoding require highly parallel and deeply pipelined decoder hardware architectures.…”