Why Can Some Advanced Ethernet NICs Cause Packet Reordering?

Wu, Wenji; DeMar, Phil; Crawford, M.

doi:10.1109/lcomm.2011.122010.102022

Cited by 27 publications

(17 citation statements)

References 2 publications

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“…For example, accurate timestamps may be necessary [19], packet disorder may be a significant inconvenient (according to the application running on the top of the engine) [18], or simply, it may be interesting to save cores for other tasks. In this scenario, PF RING DNA is clearly the best option, as it shows (almost) full rates regardless packet sizes even with only one queue (thus, avoiding any drawbacks due to parallel paths).…”

Section: Capture Engines Comparison and Discussionmentioning

confidence: 99%

“…This process of serialization when distributing traffic at user-level degrades the system's performance, since the obtained speedup at driver-level is lost. Additionally, merging traffic from different queues may entail packet disordering [18].…”

Section: Packet Capturing Limitations: Wasting the Potential Performancementioning

confidence: 99%

“…First, it requires the use of several cores for capturing purposes, cores that otherwise may be used for other tasks. Second, packets may arrive potentially out-of-order at user-level which may affect some kind of applications [18]. Third, RSS distributes traffic to each receive queue by means of a hash function.…”

Section: Proposed Techniques To Overcome Limitationsmentioning

confidence: 99%

See 2 more Smart Citations

High-Performance Network Traffic Processing Systems Using Commodity Hardware

García‐Dorado

Mata

Ramos

et al. 2013

Lecture Notes in Computer Science

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Section: Capture Engines Comparison and Discussionmentioning

confidence: 99%

Section: Packet Capturing Limitations: Wasting the Potential Performancementioning

confidence: 99%

Section: Proposed Techniques To Overcome Limitationsmentioning

confidence: 99%

See 1 more Smart Citation

High-Performance Network Traffic Processing Systems Using Commodity Hardware

García‐Dorado

Mata

Ramos

et al. 2013

Lecture Notes in Computer Science

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“…The experiment was repeated ten times to obtain mean and standard deviation for throughput and OWD. In the case of pktgen module, traffic has been generated using a single transmission queue since packet sequence numbers must be correlative for throughput and delay measurements, and using multiple queues produces packet disorder [15].…”

Section: Evaluation Testbedsmentioning

confidence: 99%

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks

et al. 2016

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Esta es la versión de autor del artículo publicado en: This is an author produced version of a paper published in: Multi-Gb/s links are becoming widespread, and network devices are under a continuous stress, so testing whether they guarantee the specified throughput or delay is a must. Software-based solutions, such as the packet-train traffic injection, were adequate for lower speeds, but they have turned inaccurate in the current scenario.Hardware-based solutions have proved to be very accurate, but usually at the expense of much higher development and acquisition costs. Fortunately, the new affordable FPGA SoC devices, as well as highlevel synthesis tools, can very efficiently reduce these costs. In this paper we show the advantages of hardware-based solutions in terms of accuracy, comparing the results obtained in an FPGA SoC development platform and in NetFPGA-10G to those of software. Results show that a hardware-based solution is significantly better, especially at 10 Gb/s. By leveraging high-level synthesis and open source platforms, prototypes were quickly developed. Noticeable advantages of our proposal are the high accuracy, the competitive cost with respect to the software counterpart, which runs in high-end off-the-shelf workstations, and the capability to easily evolve to upcoming 40 Gb/s and 100 Gb/s networks.

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“…A flow group is the set of network flows with an identical RETA index. The host updates the table using PCIe writes on a distinct control path, which can lead to packet reordering [52].…”

Section: Dynamic Nic Configurationmentioning

confidence: 99%

Energy proportionality and workload consolidation for latency-critical applications

Prekas

Primorac

Belay

et al. 2015

Proceedings of the Sixth ACM Symposium on Cloud Computing

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Energy proportionality and workload consolidation are important objectives towards increasing efficiency in largescale datacenters. Our work focuses on achieving these goals in the presence of applications with µs-scale tail latency requirements. Such applications represent a growing subset of datacenter workloads and are typically deployed on dedicated servers, which is the simplest way to ensure low tail latency across all loads. Unfortunately, it also leads to low energy efficiency and low resource utilization during the frequent periods of medium or low load.We present the OS mechanisms and dynamic control needed to adjust core allocation and voltage/frequency settings based on the measured delays for latency-critical workloads. This allows for energy proportionality and frees the maximum amount of resources per server for other background applications, while respecting service-level objectives. Monitoring hardware queue depths allows us to detect increases in queuing latencies. Carefully coordinated adjustments to the NIC's packet redirection table enable us to reassign flow groups between the threads of a latency-critical application in milliseconds without dropping or reordering packets. We compare the efficiency of our solution to the Pareto-optimal frontier of 224 distinct static configurations. Dynamic resource control saves 44%-54% of processor energy, which corresponds to 85%-93% of the Pareto-optimal upper bound. Dynamic resource control also allows background jobs to run at 32%-46% of their standalone throughput, which corresponds to 82%-92% of the Pareto bound.

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Why Can Some Advanced Ethernet NICs Cause Packet Reordering?

Cited by 27 publications

References 2 publications

High-Performance Network Traffic Processing Systems Using Commodity Hardware

High-Performance Network Traffic Processing Systems Using Commodity Hardware

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks

Energy proportionality and workload consolidation for latency-critical applications

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