Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode
Abstract:A fully depleted silicon-on-insulator (FD SOI) device having an ultrathin buried oxide (BOX) with a 45-nm fully silicided (FUSI) NiSi gate, and a hybrid SOI/bulk complementary metal oxide semiconductor (CMOS) integration process have been developed. The optimal threshold voltage (V th ) for low stand-by power (LSTP) applications in FUSI gate silicon on thin BOX (SOTB) MOSFETs was achieved while keeping a lightly doped channel. By using back-gate bias, we have demonstrated the optimization of device power and p… Show more
“…The quality of the surface after the BOX removal is a concern in this process. Carrier mobilities as high as a universal curve and gate oxide interface trap density (D it ) as low as 10 11 eV -1 cm -2 were confirmed with no sacrificial oxidation of the surface, indicating that little damage was caused by dry etching during the SOI-layer removal (Ishigaki et al, 2008). A sufficiently long time-dependent dielectric breakdown (TDDB) lifetime is ensured at V g = 3.3 V, as shown in Fig.…”
Section: Device Design and Fabricationmentioning
confidence: 72%
“…To solve the V th variation problem due to RDF and satisfy the demand from circuit designers, we have proposed the SOTB CMOSFET (Tsuchiya et al, 2004;Ishigaki et al, 2008;Morita et al, 2008). Figure 1 shows a schematic cross-section of the SOTB structure.…”
“…The quality of the surface after the BOX removal is a concern in this process. Carrier mobilities as high as a universal curve and gate oxide interface trap density (D it ) as low as 10 11 eV -1 cm -2 were confirmed with no sacrificial oxidation of the surface, indicating that little damage was caused by dry etching during the SOI-layer removal (Ishigaki et al, 2008). A sufficiently long time-dependent dielectric breakdown (TDDB) lifetime is ensured at V g = 3.3 V, as shown in Fig.…”
Section: Device Design and Fabricationmentioning
confidence: 72%
“…To solve the V th variation problem due to RDF and satisfy the demand from circuit designers, we have proposed the SOTB CMOSFET (Tsuchiya et al, 2004;Ishigaki et al, 2008;Morita et al, 2008). Figure 1 shows a schematic cross-section of the SOTB structure.…”
“…Figure 2 compares I d -V d characteristics of the SOTB and the bulk NMOSFETs. The SOTB device has comparable driving performance because the raised S/D structure makes the S/D resistances sufficiently low [2]. Neither kink nor self-heating effects were observed because of the FD operation due to thin SOI and thin BOX, respectively.…”
Section: A Hot Carrier Injection In Sotb Nmosfetsmentioning
confidence: 99%
“…We have proposed and developed FD-SOI CMOSFETs with an ultrathin BOX, called silicon on thin BOX (SOTB) as a solution (Fig. 1) [1][2][3][4]. In addition to its superior scalability, another significant feature is the back-bias controllability through the thin BOX (t BOX ~ 10 nm), whose flexibly optimizes the performance without increasing standby leakage currents.…”
Hot carrier injection (HCI) and negative bias temperature instability (NBTI) of fully depleted silicon-oninsulator (FD-SOI) CMOSFETs with thin-buried oxide (BOX) were investigated for the first time. A comparison with conventional bulk devices showed that no halo implant in this structure produces better reliability. The impact of back-biasing in thin-BOX FD-SOI devices on reliability is also reported.
“…We previously showed that the SOTB has wide-range V th controllability thanks to the thin BOX and demonstrated that the chip-to-chip bias control can reduce global variation of V th and off-state-current across a wafer. 4) Then we showed that it has a small V th variation that is about half that of the conventional bulk CMOS. 5) In this study, we systematically investigated the V th variation of SOTB using a variety of samples and estimated to what extent a small V th variation decreases the leakage current.…”
Threshold-voltage (V th ) variation of silicon on thin buried oxide (SOTB) complementary metal-oxide-semiconductor (CMOS) transistors and the impact of reducing the variation on leakage current were studied. Both reduction of impurity concentration in the silicon-on-insulator (SOI) layer and suppression of short-channel effect without the halo implantation were essential for reducing the V th variation. Using a metal-gate was also effective. The standard deviation of V th (V th ) for SOTB with fully silicided (FUSI) metal gate was half that for the bulk with the same gate size. This improvement can reduce the off-state leakage current summed over a large number of transistors by half in the 65-nm technology. With further scaling of the gate length, this effect can be enhanced. The SOTB of small V th has a strong impact on reducing leakage current in highly scaled LSI. #
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