Wire sizing with scattering effect for nanoscale interconnection

Shian,; Jian, Pan

doi:10.1109/aspdac.2006.1594735

Cited by 7 publications

(4 citation statements)

References 30 publications

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“…Although the thickness for the global interconnect decreases more slowly than the width, the line resistance continues to increase at each generation. As the technology scales below 65nm, wires width becomes a small multiple of the mean free path of electrons which is roughly 40nm [48] for copper at room temperature and the scattering effect exacerbates the trend of growing wire resistance. In Table 1.1 and Figure 1.1, we see a significant increase in the line resistance beyond 65nm.…”

Section: Scaling Issuesmentioning

confidence: 99%

On‐Chip Surfing Interconnect

Yang¹,

Greenstreet²

2012

Advanced Circuits for Emerging Technologies

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With growing chip sizes and operating frequencies, on-chip global interconnect has become a critical bottleneck for CMOS technology. With processes scaling into deep submicron scales, the gap between gate delay and globalinterconnect delay increases with each technology generation. Bandwidth is also important for on-chip interconnect and is limited by skew and jitter. Due to temperature variation, crosstalk noise, power supply variation and parameter variation, timing variation increases with the length of global interconnect lines. Jitter and skew in the transmitter and receiver's clocks add timing variation to on-chip interconnect communication. Repeaters in a buffering technique amplify clock jitter and drop pulses due to intersymbol interference. Latches can be inserted in place of some of the buffers to control the timing variation. However, these latches increase latency and power consumption. In 2002, a novel circuit technique called "surfing" was proposed to bound the timing uncertainty in wave pipelines [57]. This thesis extends the application of surfing to on-chip interconnects and introduces surfing RC interconnect and surfing LC interconnect techniques. For RC interconnects, we present a jitter attenuating buffer. This buffer uses inverters with variable output strength to implement a simple, lowgain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interconnect. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication. We use distributed varactors to dynamically vary the latency of LC interconnects and thus effect surfing. Different from RC signaling, signals on LC interconnect propagate at nearly the speed-of-light. The varactors not only modulate the line latency, but also sharpen the edges of signals. We present both a full-swing and a low-swing LC interconnect designs. In both interconnects, the jitter and skew are attenuated along the line due to the surfing effect. In the low swing interconnect, the surfing effect also helps to reshape the pulses to increase the eye height. To demonstrate these techniques in real silicon, we designed, fabricated and tested a chip. The testing Without extensive support, discussion and endless encouragement from Dr. Mark Greenstreet, this work would not have been possible. Most importantly, Dr. Mark Greenstreet tries every possible way to help me to enjoy this work and make my stay at Vancouver to be such a wonderful time. He and his family, Susan Greenstreet, Laura Greenstreet and Jenny Greenstreet impress me a lot by their sense of humor to the world. I would not have completed the chip design without the support and help from the member of VLSI research group in SUN Microsystems Laboratory. Special thanks goes to Dr. Robert Drost, who triggers the idea of varactors used in the surfing interconnect, Alex Chow for a lot of discussions on Varactors and line parameters and helps on chip testing, Justin...

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Section: Scaling Issuesmentioning

confidence: 99%

On‐Chip Surfing Interconnect

Yang¹,

Greenstreet²

2012

Advanced Circuits for Emerging Technologies

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“…Based on curve fitting techniques, Ref. [8] has proposed the analytical model to predict the resistivity of copper with consideration of scattering effect:…”

Section: The Delay-bandwidth Considering Scattering Effect 21 Delaymentioning

confidence: 99%

“…With consideration of scattering effect, the optimisation model of the line width for delay has been proposed in Ref. [8]. However, with the increasing signal frequency and the reducing rise time, bandwidth has become one of the key factors to be considered when we design a global interconnect.…”

Section: Introductionmentioning

confidence: 99%

An interconnect width and spacing optimization model considering scattering effect

2010

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As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.

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“…For our calculations, we assumed 32nm technology, with the last stage driver being 3.2 µm wide. The driver resistance and capacitance values are given in [29]. The 2 µm interconnect pitch links were assumed to be of 100 µm trace width while the 10 µm interconnect pitch links were assumed to be of 500 µm trace width.…”

Section: Superchips Benefitsmentioning

confidence: 99%

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Jangam

Pal

Bajwa

et al. 2017

2017 IEEE 67th Electronic Components and Technology Conference (ECTC)

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Abstract-In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small dielets (1-25 mm 2 ) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Our simulations show that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and low cross-talk (<-15 dB). With fine interconnect pitches (<10 μm), our scheme can achieve >5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore our protocol is simple and non-proprietary. We show that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.

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Wire sizing with scattering effect for nanoscale interconnection

Cited by 7 publications

References 30 publications

On‐Chip Surfing Interconnect

On‐Chip Surfing Interconnect

An interconnect width and spacing optimization model considering scattering effect

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

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