The optimization of wire size has become a key technology for improving the chip system performance. Based on the influence of the wire size of interconnects on the delay, power, area and bandwidth, we propose an idea of optimal wire size based on multi-objective optimization method and obtain a multi-objective constrained analytical model by curve-fitting approach. The Hspice verification shows that the analytical model presented in this paper has a high precision and the average error is less than 5%. The algorithm is simple and can effectively compensate for deficiencies in application of quality factor approach and it can be applied to computer-aided design of nano-scale complementary metal-oxide semiconductor (CMOS) system chips.

As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.

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