An optimization model of wire size for multi-objective constraint

Based on a stochastic wire length distributed model, the reduction in the length of interconnects and gate pitch for three-dimensional (3D) integrated circuit is predicted exactly. Using the results of this model, the impact of increasing of the number of active layers on the system performance in term of the product of delay and power dissipation is evaluated. Comparative results with a two-dimensional (2D) integrated circuit show the system performance of 3D circuit with two active layers is improved at least 50% at sacrifice of 10% chip temperature, demonstrating 3D integration advantage in future integrated circuit design.

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Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit

Dong¹,

Wen-Shan²,

Yang³

2015

Acta Phys. Sin.

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Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5% delay penalty.

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An optimization model of wire size for multi-objective constraint

Cited by 3 publications

References 9 publications

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

System level performance evaluation of three-dimensional integrated circuit

Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit

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