Wireless Interchip Interconnects

Abstract

IntroductionAccording to the scaling rule of metal-oxide-semiconductor (MOS) transistors in silicon large-scale integrated circuits (LSIs), both operating frequency and power consumption can be improved by reducing the feature sizes of MOS transistors, as shown in Table 15.1 [1]. A system on a chip (SOC) has been developed because it enables the highest packing density of scaled transistors for building an ultra-large-scale integrated circuit system (ULSI). However, the scaling of metal interconnects in an SOC deteriorates the performance of the LSI system because it increases resistance-capacitance (RC) time constants in the metal interconnects, as shown in Table 15.2 [2, 3]. To solve the RC signal delay problems for advanced CMOS technology, new materials such as copper (Cu) and low dielectric constant (low-k) interlayer dielectric films have been introduced [4, 5], as shown in Figure 15.1 (a). Figures 15.1 (b) and (c) are schematic diagrams of complementary MOS (CMOS) inverter circuits connected with a metal interconnect line and its equivalent circuit, respectively [2, 3]. The rise time T 90 % of the output digital signal is expressed aswhere R int , R tr , C int and C L are interconnect resistance, transistor output resistance, interconnect capacitance and load capacitance, respectively. Although the new materials can reduce