2014
DOI: 10.1049/joe.2013.0209
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Wireless network‐on‐chip: a survey

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Cited by 27 publications
(15 citation statements)
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“…It can be any of the conventional NoC topologies, such as mesh, tree, ring etc. The upper level of the network contains hubs connected by both wired and wireless links [5].…”
Section: A Topologymentioning
confidence: 99%
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“…It can be any of the conventional NoC topologies, such as mesh, tree, ring etc. The upper level of the network contains hubs connected by both wired and wireless links [5].…”
Section: A Topologymentioning
confidence: 99%
“…Such architecture enhances scalability and simulation results show that the energy/bit for OWN is 30.36% lower than wireless and 13.99% higher than photonic architecture. Several studies [4], [5] have made preliminary comparisons among these different interconnect technologies. Table I gives an overview of the main advantages and limitations of the interconnect technologies mentioned previously.…”
Section: Introductionmentioning
confidence: 99%
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“…In another study [23], a 3D Torus ONoC along with an adaptive routing algorithm has been proposed for improving the performance of 3-D ONoCs. In [24], 3D-NoC, Photonic NoC and WiNoC have been compared. The study of these methods indicates that these approaches, given their unique characteristics, can solve the problems caused by scalability in NOC; however, they have some requirements for design and manufacturing which must be further investigated [5].…”
Section: Related Workmentioning
confidence: 99%
“…Instead, for the antenna, there are still open issues on optimizing the trade-off between area, gain and bandwidth. For example, the survey work [56] also declares that the on-chip antenna is still one of the most difficult components to integrate on-chip. Moreover, [56] declares that, although implementations of on-chip antennas have been proposed and studied in literature, there are still many challenges in manufacturing and integrating them in terms of area, performance, and energy overheads, especially as the number of on-chip cores will be scaling up in the future.…”
Section: Introductionmentioning
confidence: 99%