Wirelessly powered and bidirectional data exchanged in smart medical microsystems

Hu, Yamu; Coulombe, J.

doi:10.1109/cicc.2005.1568596

Cited by 17 publications

(6 citation statements)

References 9 publications

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“…8. Therefore, the value of is a capacitive ratio of as (8) Initially, since is in the cut-off region, capacitances and are almost the same and equal to the overlapping capacitance. The value of is thus about half of .…”

Section: B Self Start-up Mechanismmentioning

confidence: 96%

“…The full-wave rectifier typically uses diodes or diode-connected transistors to ensure that a unidirectional current can flow into the output. However, when the full-wave rectifier has either two series diodes [8] or one diode-connected transistor [9], [10] along the conducting path, the value of due to the diode forward-biased voltage or threshold voltage of the transistor would limit the voltage conversion ratio. Recently, active-diode rectifiers have been reported to maximize the voltage conversion ratio [11], [12], in which all four power transistors are driven on as switches and off completely to minimize the value of .…”

Section: Introductionmentioning

confidence: 98%

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An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants

Guo

Lee

2009

IEEE J. Solid-State Circuits

229

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This paper presents an efficiency-enhanced integrated full-wave CMOS rectifier for the transcutaneous power transmission in high-current biomedical implants. The comparator-controlled switches are developed to minimize the voltage drop along the conducting path while achieving the unidirectional current flow. The proposed unbalanced-biasing scheme also minimizes the reverse leakage current of the rectifier under different input amplitudes, thereby optimizing the rectifier power efficiency. Moreover, the proposed rectifier is able to self start and operates at low input amplitudes. Implemented in a standard 0.35 m CMOS process with maximum threshold voltages of thp = 0 82 V and thn = 0 69 V, the rectifier can source a maximum output current of 20 mA and operate properly with inputs of different amplitudes and frequencies. With a 1.5 MHz input of 1.2 V amplitude, the proposed rectifier can achieve the peak voltage conversion ratio of 95% and the power efficiency of at least 82%.

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Section: B Self Start-up Mechanismmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 98%

An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants

Guo

Lee

2009

IEEE J. Solid-State Circuits

229

View full text Add to dashboard Cite

show abstract

“…In this way to improve the efficiency, modified connections of MOS based full-wave centre-tapped rectifiers are designed with better configurations which could also reduced the leakage power dissipation with impressive results and forward voltage drop across the modified MOS [22]. Due to this, output voltage couldn't be reduced up to the evaluating level [23]. So, the efficiency could be improved.…”

Section: Evaluation Of Mos Based Full-wave Centre-tapped Rectifier CImentioning

confidence: 99%

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

Jain

Akashe

2016

Wireless Pers Commun

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A novel, more competent, low leakage and comparatively high speed full-wave centre-tapped rectifier is introduced with minimum distortion. Proficient and exploratory combinations of PMOS-PMOS or NMOS-NMOS logic are utilized to design full-wave centre-tapped rectifier. The scrupulous PMOS-PMOS logic with augmented stacked NMOS transistor is communal form of two PMOS and one NMOS transistor. The main motive of manipulating these circuits is to maintain the substrate biasing during circuit operation. The substrate biasing refers the exploitation in which substrate and drain/source terminal of a transistor is kept in reverse biasing mode. Due to utilization of modified MOS structure after replacing of diode, efficiency of full-wave centre-tapped rectifier is increased up to 20 % with compare to p-n junction diode based full wave centre-tapped rectifier and leakage power dissipation is reduced up to 57 %. The proposed circuit is designed to utilize the body effect properly to reduce the total leakage power of the circuit. The novelty of proposed circuit is the uniqueness of combination of MOS. Due to this; the proposed circuit has impressive resultant parameter with compare to other circuits and previous results. Proposed MOS based full-wave centre-tapped rectifier is optimized at 45 nm CMOS technology and cadence simulation experimental implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.

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“…Even there are differences in process parameters, high CMRR can be obtained [26]. Instrumentation amplifier using operational amplifier has the advantage of very small chip area, so it is suitable for implantable applications [27]. The CMRR of instrumentation amplifier optimized through operational amplifier is comparative not good.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of Two-Stage Differential Amplifier with Stacked Transistors for Biomedical Applications

Jain¹,

Sharma

Joshi

2021

Preprint

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In this paper, CMOS based optimized two stage differential amplifier circuit for convenient biomedical signal conditioning system is presented. A low-power, low noise & high CMRR differential amplifier is designed for portable ECG signal conditioning using MOS based low pass filter with stacked transistors. The stack transistors with MOS which is connected at output terminal optimize the design for ECG signal conditioning and other biomedical device signal conditioning. The presented amplifier is designed with standard 45nm CMOS process technology at a 0.85 V supply voltage. The simulation results are derived using Cadence Analog Virtuoso Spectre Simulator. The simulation results show that the presented differential amplifier has a common-mode rejection ratio (CMRR) of 178dB at 100Hz, power supply rejection ratio (PSRR) of 68 dB and power dissipation of 1.5μW. The input referred (IR) noise is 3.83μV/√f and slew rate is 11volt/μsec. These obtained performance parameters is better and efficient compared to conventional differential amplifier. The noise performance is improved using proposed design compared to previous designed differential amplifier.

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Wirelessly powered and bidirectional data exchanged in smart medical microsystems

Cited by 17 publications

References 9 publications

An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants

An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier

Design of Two-Stage Differential Amplifier with Stacked Transistors for Biomedical Applications

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