Wiring Effect Optimization in 65-nm Low-Power NMOS

Abstract

This letter investigates the wiring effect on RF performance in advanced 65-nm low-power CMOS technology. New designs are proposed to minimize the parasitic resistances and capacitances associated with the interconnects in the transistor. Compared with the standard multifinger devices provided by the foundry, the device with the optimized wiring parasitic capacitances and resistances presents improvement up to ∼21% for f T (increased from 89 to 108 GHz) and ∼22% for f max (increased from 130 to 159 GHz), respectively. The extracted equivalent circuit model parameters indicate that the proposed approach can effectively minimize the parasitic effects leading to improved RF performance of the advanced MOSFETs.

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“…The parasitics can also be reduced by the interconnect layout in the transistors. The wiring effect could be significant on the corresponding parasitic capacitances and resistances www.intechopen.com especially for advanced technology with a small feature size (Chan et al, 2008). For transistors with a small gate length such as 65 nm, the parasitics originated from the transistor interconnects are critical to the overall frequency response.…”