Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Agarwal

Dolecek

et al. 2013

138

116

Abstract-Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software. This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. The envisioned underdesigned and opportunistic computing (UnO) machines face a number of challenges related to the sensing infrastructure and software interfaces that can effectively utilize the sensory data. In this paper, we outline specific sensing mechanisms that we have developed and their potential use in building UnO machines.

Section: Adjusting Hardware Operating Pointmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Agarwal

Dolecek

et al. 2013

138

116

“…Process variation has die-todie (D2D) and within-die (WID) components [2]. A recent experimental Intel processor shows around 50% performance variation among its 80 cores when operated at 0.8V due to WID process variation alone [3]. As for the environmental variations, International Technology Roadmap for Semiconductors (ITRS) projects supply power variation to be 10% while the operating temperature can vary from 30 to 175…”

Section: Introductionmentioning

confidence: 99%

Timing analysis of erroneous systems

Assare

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

2014

Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter-and Intra-Program Variation as measures of error rate variability in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.

“…Though variability measurements through simple silicon test structures abound (e.g., [8], [9]), variability characterization of full components and systems have been scarce. Moreover, such measurements have been largely limited to processors (e.g., 14X variation in sleep power of embedded microprocessors [6] and 25% performance variation in an experimental 80-core Intel processor [10]). For a large class of applications, memory power is significant (e.g., 48% of total power in [11]) which has motivated several efforts to reduce dynamic random access memory (DRAM) power consumption (e.g., power-aware virtual memory systems [12]- [14]).…”

mentioning

confidence: 99%

Power Variability in Contemporary DRAMs

Gottscho

Kagalwalla

IEEE Embedded Syst. Lett.

2012

Abstract-Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the 50 C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.Index Terms-Double data rate third generation (DDR3), dynamic random access memory (DRAM), power, variability.