WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

Yavits, Leonid; Orosa, Lois; Mahar, Suyash; Ferreira, João Dinis; Erez, Mattan; Ginosar, Ran; Mutlu, Onur

doi:10.1109/iccd50377.2020.00044

Cited by 11 publications

(5 citation statements)

References 83 publications

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“…They range from working on fine-grained levels [4]- [6], [11] to coarse-grained memory blocks [7]- [9] or even with multiple granularities like [10], [13]. To improve memory lifetime, the previous works used either aging-aware strategies, e.g., [16], [17], [21]- [23], or non-aging-aware strategies, e.g., [11], [15], [24]. For the completeness, we select some representatives to review their insights and thus position our work in the following.…”

Section: Related Workmentioning

confidence: 99%

“…Alternatively, software-based approaches, which are relatively more portable, have been more attractive. WoLFRAM uses a programmable resistive address decoder to change the address and swap it in a write-access-pattern aware manner, by adding one specific controller for each memory bank [23]. Hakert et al proposed to use a red-black tree to maintain the estimated age of physical memory pages without special hardware supports [14].…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Hölscher

Hakert

Nassar

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Emerging non-volatile memory yields, alongside many advantages, technical shortcomings, such as reduced cell lifetime. Although many wear-leveling approaches exist to extend the lifetime of such memories, usually a trade-off for the granularity of wear-leveling has to be made. Due to iterative write schemes (repeatedly sense and write), wear-out of memory in certain systems is directly dependent on the written bit value and thus can be highly imbalanced, requiring dedicated bit-wise wear-leveling. Such a bit-wise wear-leveling so far has only be proposed together with a special hardware support. However, if no dedicated hardware solutions are available, especially for commercial off-the-shelf systems with non-volatile memories, a software solution can be crucial for the system lifetime.In this work, we propose entirely software-based bit-wise wearleveling, where the position of bits within CPU words in main memory is rotated on a regular basis. We leverage the LLVM intermediate representation to adjust load and store operations of the application with a custom compiler pass. Experimental evaluation shows that the lifetime by applying local rotation within the CPU word can be extended by a factor of up to 21×. We also show that our method can incorporate with coarser-grained wear-leveling, e.g. on block granularity and assist achievement of higher lifetime improvements.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Hölscher

Hakert

Nassar

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Many prior works [51], [56], [60], [79], [228], [229], [232], [233], [235], [251], [252], [253], [254], [255], [256], [257], [258], [259] aim to reduce the impact of emerging NVMs on overall system energy consumption and lifetime. The great majority of such works aim to (i) reduce the number of write operations the system issue to the NVM device using techniques such as caching [51], [79], writeaware data mapping and data allocation algorithms [60], [79], [229], and data compression [228]; and (ii) distribute write operations across NVM cells using diverse wear-leveling techniques [56], [232], [233], [235], [251], [253], [254], [255], [256], [257], [259]. We believe such approaches can be employed to mitigate the limitations of NVMs in consumer devices.…”

Section: A Overall Limitations Of the Technologymentioning

confidence: 99%

Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD

Oliveira,

Ghose,

Gómez-Luna

et al. 2023

IEEE Access

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DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We equip real web-based Chromebook computers with the Intel Optane solid-state drive (SSD), which contains state-of-the-art low-latency NVM, and use the NVM as swap space. We analyze the performance and energy consumption of the Optane-equipped Chromebooks, and compare this with (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-theart NAND-flash-based SSD. Our experimental analysis reveals that while Optane-based swap space provides a cost-effective way to alleviate the DRAM capacity bottleneck in consumer devices, naive integration of the Optane SSD leads to several system-level overheads, mostly related to (1) the Linux block I/O layer, which can negatively impact overall performance; and (2) the off-chip traffic to the swap space, which can negatively impact energy consumption. To reduce the Linux block I/O layer overheads, we tailor several system-level mechanisms (i.e., the I/O scheduler and the I/O request completion mechanism) to the currentlyrunning application's access pattern. To reduce the off-chip traffic overhead, we leverage an operating system feature (called Zswap) that allocates some DRAM space to be used as a compressed in-DRAM cache for data swapped between DRAM and the Intel Optane SSD, significantly reducing energy consumption caused by the off-chip traffic to the swap space. We conclude that emerging NVMs are a cost-effective solution to alleviate the DRAM capacity bottleneck in consumer devices, which can be further enhanced by tailoring system-level mechanisms to better leverage the characteristics of our workloads and the NVM.

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“…1 and 3 show a vulnerable DRAM cell experiences bit flips at a particular temperature range. To improve a DRAM chip's reliability, the system might incorporate a mechanism to temporarily or permanently retire DRAM rows (e.g., via software page offlining [92] or hardware DRAM row remapping [15,168]) that are vulnerable to RowHammer within a particular operating temperature range. To adapt to changes in temperature, the row retirement mechanism might dynamically adjust the rows that are retired, potentially leveraging previously-proposed techniques (e.g., Rowclone [134], LISA [18], NoM [125], FIGARO [154]) to efficiently move data between these rows.…”

Section: Potential Defense Improvementsmentioning

confidence: 99%

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

Orosa

Yağlıkçı

Luo

et al. 2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability worsens as DRAM cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern DRAM chips, including chips previously marketed as RowHammer-safe, are even more vulnerable to RowHammer than older chips such that the required hammer count to cause a bit flip has reduced by more than 10X in the last decade. Therefore, it is essential to develop a better understanding and in-depth insights into the RowHammer vulnerability of modern DRAM chips to more effectively secure current and future systems.Our goal in this paper is to provide insights into fundamental properties of the RowHammer vulnerability that are not yet rigorously studied by prior works, but can potentially be 𝑖) exploited to develop more effective RowHammer attacks or 𝑖𝑖) leveraged to design more effective and efficient defense mechanisms. To this end, we present an experimental characterization using 248 DDR4 and 24 DDR3 modern DRAM chips from four major DRAM manufacturers demonstrating how the RowHammer effects vary with three fundamental properties: 1) DRAM chip temperature, 2) aggressor row active time, and 3) victim DRAM cell's physical location. Among our 16 new observations, we highlight that a RowHammer bit flip 1) is very likely to occur in a bounded range, specific to each DRAM cell (e.g., 5.4% of the vulnerable DRAM cells exhibit errors in the range 70 °C to 90 °C), 2) is more likely to occur if the aggressor row is active for longer time (e.g., RowHammer vulnerability increases by 36% if we keep a DRAM row active for 15 column accesses), and 3) is more likely to occur in certain physical regions of the DRAM module under attack (e.g., 5% of the rows are 2x more vulnerable than the remaining 95% of the rows). Our study has important practical implications on future RowHammer attacks and defenses. We describe and analyze the implications of our new findings by proposing three future RowHammer attack and six future RowHammer defense improvements.

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WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

Cited by 11 publications

References 83 publications

Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory

Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

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