Word-Level Sequential Memory Abstraction for Model Checking

Bjesse, Per

doi:10.1109/fmcad.2008.ecp.20

Cited by 10 publications

(9 citation statements)

References 12 publications

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“…We will use the STS shown in Fig. 1(a) as a running example throughout the paper (it is inspired by the hardware example from [10]). We assume the background theory T includes integer arithmetic and arrays of integers indexed by integers.…”

Section: Using Auxiliary Variables To Assist Inductionmentioning

confidence: 99%

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Counterexample-Guided Prophecy for Model Checking Modulo the Theory of Arrays

Mann

Irfan

Griggio

et al. 2021

Tools and Algorithms for the Construction and Analysis of Systems

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We develop a framework for model checking infinite-state systems by automatically augmenting them with auxiliary variables, enabling quantifier-free induction proofs for systems that would otherwise require quantified invariants. We combine this mechanism with a counterexample-guided abstraction refinement scheme for the theory of arrays. Our framework can thus, in many cases, reduce inductive reasoning with quantifiers and arrays to quantifier-free and array-free reasoning. We evaluate the approach on a wide set of benchmarks from the literature. The results show that our implementation often outperforms state-of-the-art tools, demonstrating its practical potential.

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Section: Using Auxiliary Variables To Assist Inductionmentioning

confidence: 99%

“…There are two important related approaches for abstracting arrays in horn clauses [53] and memories in hardware [10]. Both make a similar observation that arrays can be abstracted by modifying the property to maintain values at only a finite set of symbolic indices.…”

Section: Related Workmentioning

confidence: 99%

Counterexample-Guided Prophecy for Model Checking Modulo the Theory of Arrays

Mann

Irfan

Griggio

et al. 2021

Tools and Algorithms for the Construction and Analysis of Systems

View full text Add to dashboard Cite

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“…Existing approaches in the hardware domain perform data symmetry reduction and data type reduction through the use of bit-width reduction preprocessing passes or syntactic restrictions such as scalarsets [8,20,28]. There have also been abstraction-refinement loop algorithms proposed to handle memory symmetries [9]. All of these approaches are focused on symmetries present in the transition system description, such as the presence of large data types.…”

Section: Definition 1 a Synchronous Transition System (Sts) Is A Tupmentioning

confidence: 99%

“…We cannot use scalarsets to break symmetries in the memory addresses because the pointers index the memory and are involved in arithmetic, breaking the syntactic requirements for scalarsets [28]. Furthermore, sequential memory abstraction [9] could reduce the size of the memory, but does not address the path symmetry. In addition, both these symmetry reduction techniques are focused on proofs, not bug-finding.…”

Section: Packet Moversmentioning

confidence: 99%

Partial Order Reduction for Deep Bug Finding in Synchronous Hardware

Mann

Barrett

2020

Tools and Algorithms for the Construction and Analysis of Systems

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Symbolic model checking has become an important part of the verification flow in industrial hardware design. However, its use is still limited due to scaling issues. One way to address this is to exploit the large amounts of symmetry present in many real world designs. In this paper, we adapt partial order reduction for bounded model checking of synchronous hardware and introduce a novel technique that makes partial order reduction practical in this new domain. These approaches are largely automatic, requiring only minimal manual effort. We evaluate our technique on open-source and commercial packet mover circuitsdesigns containing FIFOs and arbiters.

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“…Our encoding of memories and bit-vectors is conceptually different from known SMT-and FOL-based techniques, as well as from the smart memory abstraction techniques seen in [9], [17], [13], [5]. It results in formulas in the decidable fragment of first-order logic known as EPR formulas or the Bernais-Schönfinkel class.…”

Section: Introductionmentioning

confidence: 98%

Verifying equivalence of memories using a first order logic theorem prover

Khasidashvili

Kinanah

Воронков

2009

2009 Formal Methods in Computer-Aided Design

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We propose a new method for equivalence checking of RTL and schematic descriptions of memories using translation into first-order logic. Our method is based on a powerful abstraction of memories and address decoders within them. We propose two ways of axiomatizing some of the bit-vector operations, decoders, and memories. The first axiomatization uses an algebra of operations on bit-vectors. The second axiomatization considers a bit-vector as a unary relation and memory as a relation of larger arity. For some designs, including real-life designs, the second axiomatization results in a first-order problem falling into a known decidable fragment of first-order logic and suitable for solving by modern first-order provers. Equivalence of real-life memories can be verified in seconds with our approach.

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Word-Level Sequential Memory Abstraction for Model Checking

Cited by 10 publications

References 12 publications

Counterexample-Guided Prophecy for Model Checking Modulo the Theory of Arrays

Counterexample-Guided Prophecy for Model Checking Modulo the Theory of Arrays

Partial Order Reduction for Deep Bug Finding in Synchronous Hardware

Verifying equivalence of memories using a first order logic theorem prover

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