Wordline voltage generating system for low-power low-voltage flash memories

Tanzawa, Toru; Umezawa, Akira; Kuriyama, M.; Taura, Toshiharu; Banba, H.; Miyaba, T.; Shiga, H.; Takano, Yoshimichi; Atsumi, S.

doi:10.1109/4.896229

Cited by 26 publications

(17 citation statements)

References 8 publications

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“…5. Block diagram of the conventional WL generating circuit [12], [13]. BGR always works in standby mode and will dissipate a current I 3 of 300 nA.…”

Section: B Novel Sl Voltage Compensation Circuitmentioning

confidence: 99%

A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded <sc>nor</sc> Flash Memory

Zhang

Jun

Yang

et al. 2014

IEEE Trans. Circuits Syst. II

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Key blocks used for embedded NOR Flash memory are introduced in this brief, including a novel sourceline (SL) voltage compensation circuit and a wordline (WL) voltage-generating system. The SL voltage compensation circuit controls the output voltage of the charge pump according to the number of cells to be programmed with data "0" to compensate the IR drop on the SL decoding path. Thus, a stable SL voltage is obtained and high program efficiency with low program disturb is realized. In order to get low power consumption in standby mode and high speed in active mode, a high-performance WL voltage-generating system has been proposed. A 1.8-V 64 × 32 kb embedded NOR Flash memory employing the two techniques has been developed based on a GSMC 0.18-μm 4-poly 4-metal CMOS process. Average standby current of the embedded Flash memory IP circuit less than 0.3 μA is achieved at 1.8 V and 25 • C.

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“…5. Block diagram of the conventional WL generating circuit [12], [13]. BGR always works in standby mode and will dissipate a current I 3 of 300 nA.…”

Section: B Novel Sl Voltage Compensation Circuitmentioning

confidence: 99%

A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded <sc>nor</sc> Flash Memory

Zhang

Jun

Yang

et al. 2014

IEEE Trans. Circuits Syst. II

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“…The main drawback in these designs is the higher number of stacked pMOS devices that influence circuit performance. Finally, a level converter that is capable to operate efficiently at a lower voltage than the nominal technology voltage is shown in [21], while in [1] an improved version of this circuit for low-voltage operation has been presented. However, as in the first case [17], the drawback of these two designs is that the technology must support dual-threshold-voltage high-voltage transistors.…”

Section: Introductionmentioning

confidence: 99%

A Stress-Relaxed Negative Voltage-Level Converter

Tsiatouhas

2007

IEEE Trans. Circuits Syst. II

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In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-m triple-well standard CMOS technology, using double-gate-oxidethickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of 3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported. Index Terms-Embedded negative voltage-level converter, level shifter, level conversion, MOS-device voltage stress relaxation.

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“…Some LSIs exist that include analog circuits that operate even after power-up [4][5][6]. The POR signal also starts up analog circuit system.…”

Section: Introductionmentioning

confidence: 99%

A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage

Tanzawa

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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A process-and temperature-tolerant power-on reset (POR) circuit is described. The operation principle of the POR circuit is based on a Kuijk cell bandgap reference with one resistor added to enable a designed output voltage higher than the Bandgap voltage of 1.25V. A test circuit with a detection level of 2.0V was fabricated and measured with a temperature variation of 19mV from 25°C to 90°C and a standard deviation of 25mV across one wafer. The circuit occupies 0.064mm 2 and dissipates 1.2μA at 90°C.

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Wordline voltage generating system for low-power low-voltage flash memories

Cited by 26 publications

References 8 publications

A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded <sc>nor</sc> Flash Memory

A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded <sc>nor</sc> Flash Memory

A Stress-Relaxed Negative Voltage-Level Converter

A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage

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