2016
DOI: 10.1016/j.solmat.2016.05.045
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Working principle of carrier selective poly-Si/c-Si junctions: Is tunnelling the whole story?

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Cited by 191 publications
(167 citation statements)
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“…For a wafer thickness of 165 μm, the estimated practical limit for i V oc is 748 mV according to Yoshikawa et al To achieve such values close to the practical limit, Taguchi et al claim that an ultraclean surface is needed, which was not assured for the sample preparation of this work as the HWCVD growth of μc‐SiC:H(n) was not performed in a clean room. Compared with TOPCon/POLO technology, the J 0 values of μc‐SiC:H(n)/SiO 2 passivation are among the lowest J 0 values reported in the recent past for wet‐chemically grown oxides ranging from 1.5 to 20 fA/cm 2 . The improvement in μc‐SiC:H(n)/SiO 2 passivation as compared with our former work was achieved by a convolution of an improved surface texture of the c‐Si wafer, higher c‐Si bulk lifetime, and optimized HWCVD process for the μc‐SiC:H(n) deposition.…”
Section: Discussionsupporting
confidence: 67%
“…For a wafer thickness of 165 μm, the estimated practical limit for i V oc is 748 mV according to Yoshikawa et al To achieve such values close to the practical limit, Taguchi et al claim that an ultraclean surface is needed, which was not assured for the sample preparation of this work as the HWCVD growth of μc‐SiC:H(n) was not performed in a clean room. Compared with TOPCon/POLO technology, the J 0 values of μc‐SiC:H(n)/SiO 2 passivation are among the lowest J 0 values reported in the recent past for wet‐chemically grown oxides ranging from 1.5 to 20 fA/cm 2 . The improvement in μc‐SiC:H(n)/SiO 2 passivation as compared with our former work was achieved by a convolution of an improved surface texture of the c‐Si wafer, higher c‐Si bulk lifetime, and optimized HWCVD process for the μc‐SiC:H(n) deposition.…”
Section: Discussionsupporting
confidence: 67%
“…Therefore, a high annealing temperature would be beneficial for a low interface state density D it . There is theoretical and experimental support of the picture that the interfacial oxide breaks up locally . This local break‐up does not compromise the POLO junction passivation quality as long as the pinhole size is only a few nanometers, and the pinhole areal density is in the range of ∼10 7 cm −2 .…”
Section: Experimental Results On Planar and Textured Surfacesmentioning
confidence: 88%
“…One should note that this analysis disregards a laterally inhomogeneous passivation due to pinhole formation. However, this approximation is justified for pinhole areal densities <10 7 cm −2 , where recombination is dominated by the regions where the interfacial oxide is still intact . For a doping concentration of N A = 2 × 10 18 cm −3 at the c‐Si/SiO x interface, we obtained S n,0 values of 220 cm s −1 for the (100) surface orientation and of 2400 cm s −1 for the (111) surface orientation (right axis of Fig.…”
Section: Experimental Results On Planar and Textured Surfacesmentioning
confidence: 90%
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“…Several studies have shown that increasing T a degraded the SiO x film [9][10][11][12]. However, in certain cases the SiO x degradation has been shown to be beneficial, leading to nanoscale pinholes within the SiO x film which improve the transport of free charge carriers through the SiO x film [13,14]. …”
Section: Increase Of the Annealing Temperaturementioning
confidence: 99%