World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

Garrido, Mario; Möller, Konrad; Kumm, Martin

doi:10.1109/tcsi.2018.2886626

Cited by 26 publications

(21 citation statements)

References 38 publications

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“…Previous works in Table IV do not report power metrics that could be used for a comparison. Indeed, only the most recent FFT architectures on FPGAs have started to report power consumption [6], [45].…”

Section: Comparison and Experimental Resultsmentioning

confidence: 99%

“…Twiddle factors of intermediate size (W 8 and W 16 ) are generally implemented as shift-andadd operations [4], [31]- [38]. Conversely, constant rotators [39]- [44] are not used in FFT architectures except in the case of a fully parallel implementation of the FFT [45]. W 8 , W 16 and general rotators are configured to rotate by a set of angles.…”

Section: Introductionmentioning

confidence: 99%

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The Constant Multiplier FFT

Garrido

Malagón

2021

IEEE Trans. Circuits Syst. I

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In this paper, we present a new fast Fourier transform (FFT) hardware architecture called constant multiplier (CM) FFT. Whereas rotators in previous architectures must rotate among several different angles, the CM FFT exploits the use of constant multipliers to calculate the rotations. The paper explores the 4-parallel and 8-parallel radix-2 CM FFT, which calculates the FFT entirely by using constant multipliers. Later, radices 2 k are presented, with emphasis in radix-2 4 and radix-2 5 as the best alternatives. Experimental results for a 1024-point radix-2 5 CM FFT show that the proposed approach reduces the number of block random-access memories (BRAM) and digital signal processing (DSP) slices with respect to previous approaches, while achieving the highest clock frequency for a 4-parallel FFT architecture on field-programmable gate arrays (FPGAs) reported so far.

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Section: Comparison and Experimental Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Constant Multiplier FFT

Garrido

Malagón

2021

IEEE Trans. Circuits Syst. I

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“…Fully parallel architectures contain all the butterfly units necessary for an N -point FFT, while iterative accelerators work on a smaller datapath. The former provides high performance, like the 2018 fastest FFT architecture by Garrido et al [18], but results in a large area for high values of N . For this reason, iterative architectures are usually adopted for embedded applications.…”

Section: Related Workmentioning

confidence: 99%

To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters

Bertaccini

Benini

Conti

2021

2021 IEEE 32nd International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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“…In the past, fully parallel FFTs have been employed in applications such as high definition (HD) streaming, chromatic dispersion filtering, beamspace processing and radar [4][5][6][7]. So far, only a few fully parallel architectures, viz., radix-2 k , radix-4 and split-radix (SR) have been reported in the literature either to realise high-throughput or low-energy [4][5][6][7]. The SRFFT has the least computational complexity among its peers, especially in number of non-trivial multiplications [5].…”

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confidence: 99%

“…So far, only a few fully parallel architectures, viz., radix-2 k , radix-4 and split-radix (SR) have been reported in the literature either to realise high-throughput or low-energy [4][5][6][7]. The SRFFT has the least computational complexity among its peers, especially in number of non-trivial multiplications [5]. This is quite evident in FFT size higher than 16.…”

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Low‐complexity, energy‐efficient fully parallel split‐radix FFT architecture

Hazarika

Ahamed

Nemade

2022

Electronics Letters

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Fully parallel pipelined fast Fourier transform offers the highest throughput but requires high area and power. In this work, an efficient fast Fourier transform processor based on the split-radix algorithm is presented to reduce the hardware complexity of fully parallel fast Fourier transforms. In fully parallel pipelined implementations, splitradix fast Fourier transform requires considerably more registers compared to other fast Fourier transform algorithms leading to more power consumption and high latency in spite of having the least number of multiplications among all fast Fourier transforms. To address this issue, the authors present a new data-flow graph with no non-trivial twiddle factors in the odd stages of the split-radix fast Fourier transform. This facilitates significant reduction in the number of pipelining registers and a lower latency is achieved. Further, an efficient shift-add twiddle factor multiplier is proposed based on architectural analysis and substructure sharing. A comparison of the proposed design with existing fully parallel fast Fourier transforms is carried out and it is found that the proposed method outperforms other designs. Synthesis results show that the proposed design offers 45-57% area savings and 67-74% energy savings compared to the best existing fully parallel fast Fourier transform design.Data availability statement: Data available upon reasonable request.

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World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

Cited by 26 publications

References 38 publications

The Constant Multiplier FFT

The Constant Multiplier FFT

To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters

Low‐complexity, energy‐efficient fully parallel split‐radix FFT architecture

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