Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores

Abdallah, Laure; Jan, Mathieu; Ermont, Jérôme; Fraboul, Christian

doi:10.1109/sies.2015.7185041

Cited by 18 publications

(35 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Proof 1: This directly follows from the property in [20]. If a packet of cluster B finished its transmission and in the next cycle there is no packet of M A,i ready (i.e.…”

Section: Write To Memory Scenariomentioning

confidence: 90%

“…at least its header flit arrived in R 2 ), then there is no data transfer in this cycle. As shown in [20], the worst case then occurs when the next packets of cluster B and A, respectively, arrive simultaneously, where arbitration is given to cluster B. Thus, the additional empty cycle increases the WCTT (see Fig.…”

Section: Write To Memory Scenariomentioning

confidence: 99%

“…The RC takes the largest possible interference of contending flows on each link into account and calculates a safe WCTT for individual NoC packets. Dasari et al [18], as well as Liu et al [19], extended the RC method to account for periodic NoC packets, and Abdallah et al [20] extended the original RC with additional properties to reduce pessimism. Ayed et al [11] adapt the RC for a Kalray-like NoC.…”

Section: Related Workmentioning

confidence: 99%

“…First the conditions to achieve the minimum WCTT are presented, when β ≥ β min . In [20], it is shown that the worst-case scenario for the traversal time of packets on a round robin arbitrated NoC occurs if the header of contending packets arrive simultaneously at the shared router and the respective other packet wins the round robin arbitration. Due to the flow regulation on source node it must also hold:…”

Section: Write To Memory Scenariomentioning

confidence: 99%

See 3 more Smart Citations

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the offchip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms.In this work, we target a state-of-the-art many-core processor, the Kalray MPPA. A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis. Abstract-Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip (NoC), which is used for communication among the compute cores via the off-chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. Partitioning and Analysis of theIn this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

show abstract

“…Proof 1: This directly follows from the property in [20]. If a packet of cluster B finished its transmission and in the next cycle there is no packet of M A,i ready (i.e.…”

Section: Write To Memory Scenariomentioning

confidence: 90%

Section: Write To Memory Scenariomentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Write To Memory Scenariomentioning

confidence: 99%

See 2 more Smart Citations

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

show abstract

“…Various timing approaches of NoCs have been proposed in the literature. The most relevant ones can broadly be categorized under several main classes: Scheduling Theory-based ( [8,12,13,17,18,21]), Compositional Performance Analysis (CPA)-based ( [15,19]), Recursive Calculus (RC)-based ( [1,4]) and Network Calculus-based ( [6,9,14]). However, these existing approaches suffer from some limitations, which are mainly due to:…”

Section: Context and Related Workmentioning

confidence: 99%

Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip

Giroudot

Mifdaoui

2019

Proceedings of the 27th International Conference on Real-Time Networks and Systems

View full text Add to dashboard Cite

This paper addresses the problem of worst-case timing analysis in wormhole Networks-On-Chip (NoCs). We consider our previous work [5] for computing maximum delay bounds using Network Calculus, called the Buffer-Aware Worst-case Timing Analysis (BATA). The latter allows the computation of delay bounds for a large panel of wormhole NoCs, e.g., handling priority-sharing, Virtual Channel Sharing and buffer backpressure.In this paper, we provide further insights into the tightness and computation issues of the worst-case delay bounds yielded by BATA. Our assessment shows that the gap between the computed delay bounds and the worst-case simulation results is reasonably small (70% tighness on average). Furthermore, BATA provides good delay bounds for medium-scale configurations within less than one hour. Finally, we evaluate the yielded improvements with BATA for a realistic use-case against a recent state-of-the-art approach. This evaluation shows the applicability of BATA under more general assumptions and the impact of such a feature on the tightness and computation time.

show abstract