2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE) 2012
DOI: 10.1109/date.2012.6176457
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Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling

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Cited by 4 publications
(14 citation statements)
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“…The algorithm with all stages, including details of inter-router ESC step, is presented in Appendix. Now, we can obtain LUDB from end-to-end ESC according to the proposed theorem for calculating delay bounds [3]. We have automated our proposed analytical approach as a tool for worst-case performance analysis.…”
Section: B Inter-router Escmentioning
confidence: 99%
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“…The algorithm with all stages, including details of inter-router ESC step, is presented in Appendix. Now, we can obtain LUDB from end-to-end ESC according to the proposed theorem for calculating delay bounds [3]. We have automated our proposed analytical approach as a tool for worst-case performance analysis.…”
Section: B Inter-router Escmentioning
confidence: 99%
“…As depicted in the figure, T HoL (f1,r) is equal to the maximum delay for passing packets of flow f 2 in the buffer. According to [1], the maximum delay for flow f j is bounded by Equation (3).…”
Section: Fig 4 An Example Of Buffer Sharingmentioning
confidence: 99%
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