Worst-case memory traffic analysis for many-cores using a limited migrative model

Abstract

The ratio between the number of cores and memory subsystems (i.e. banks and controllers) in many-core platforms is constantly increasing, leading to non-negligible latencies of memory operations. Thus, in order to study the worst-case execution time of an application, it is no longer sufficient to only take into account its computational requirements, but also have to be considered latencies related to its memory operations.In this paper we study a limited migrative model applied upon many-core platforms. This approach is based on a multi-kernel paradigm [3] -a promising step towards scalable and predictable many-cores, which are essential prerequisites for the integration of such systems into the real-time embedded domain. Under that assumption, we present two analytical methods to obtain the worst-case memory traffic delays of individual applications. Through experiments we test the applicability of the proposed approaches to different scenarios, and draw practical conclusions concerning routing mechanisms and a distribution of memory operations across memory controllers.

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

“…In two papers in 2013 [88] and 2015 [87] Nikolic et al study NoC-based many-core platforms. They consider the latencies of memory operations and propose two methods to obtain the upperbound on the worst-case memory traffic delays of individual applications.…”

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

“…Most analyses consider multi-core systems with a simple bus providing access to a single shared memory [9], [10], [11], [12]. However, contention analysis of clustered many-core platforms has also been explored, as in [13], [14], [15], [16], where the former two are the most relevant for this work, as they focus on Kalray MPPA-256, which is the platform considered in this paper.…”

Network-on-Chip aware scheduling of hard-real-time tasks

“…Nikolic et al [20] propose worst case off-chip memory traffic analysis under a limited migrative model. They allocate tasks onto cores and propose a technique to calculate the worstcase interference time of packets belonging to a given task.…”

“…Several techniques [22], [23], [24], [25], [26] have been proposed in recent years for static and dynamic cache locking. 2 In order to perform a fair comparison of our proposed approach to other existing NoC scheduling and analysis schemes such as the Limited Migrative Model approach proposed by Nikolic et al [20], significant adaptation of existing schemes is required due to different assumptions about task allocation and cache-related aspects. Such adaptation is out of the scope of the current paper.…”