Wrong-path instruction prefetching

Journal of Parallel and Distributed Computing

Yilmazer

et al. 2007

The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch prediction accuracy, these processors still execute many memory instructions down mispredicted paths. Previous work that focused on uniprocessors showed that these wrong-path (WP) memory references may pollute the caches and increase the amount of cache and memory traffic. On the positive side, however, they may prefetch data into the caches for memory references on the correct-path. While computer architects have thoroughly studied the impact of WP effects in uniprocessor systems, there is no comparable work for multiprocessor systems. In this paper, we explore the effects of WP memory references on the memory system behavior of shared-memory multiprocessor (SMP) systems for both broadcast and directory-based cache coherence. Our results show that these WP memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8% and 20% for broadcast and directory-based SMPs, respectively, and the number of writebacks by up to 67% for both systems. In addition to the extra coherence traffic, WP memory references also increase the number of cache line state transitions by 21% and 32% for broadcast and directory-based SMPs, respectively. In order to reduce the performance impact of these WP memory references, we introduce two simple mechanisms-filtering WP blocks that are not likely-to-be-used and WP aware cache replacement-that yield speedups of up to 37%.

Section: Related Workmentioning

confidence: 99%

“…Previous work [1,2,6,9,13,[20][21][22][23][24][25]4,[28][29][30] studied the effects that speculatively executed memory references have on the performance of out-of-order superscalar processors. These papers yield several conclusions.…”

Section: Introductionmentioning

confidence: 99%

The impact of wrong-path memory references in cache-coherent multiprocessor systems

Journal of Parallel and Distributed Computing

Yilmazer

et al. 2007

“…While several other prefetching schemes have been proposed, such as adaptive sequential prefetching [11], prefetching with arbitrary strides [11,14], fetch directed prefetching [13], and selective prefetching [15], Pierce and Mudge [20] have proposed a scheme called wrong path instruction prefetching. This mechanism combines next-line prefetching with the prefetching of all instructions that are the targets of branch instructions regardless of the predicted direction of conditional branches.…”

Section: Related Workmentioning

confidence: 99%

“…Several methods have been proposed to exploit more instruction-level parallelism in superscalar processors and to hide the latency of the main memory accesses, including speculative execution [1][2][3][4][5][6][7] and data prefetching [8][9][10][11][12][13][14][15][16][17][18][19][20][21]. To achieve high issue rates, instructions must be fetched beyond the basic block-ending conditional branches.…”

Section: Introductionmentioning

confidence: 99%

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

Euro-Par 2002 Parallel Processing

Lilja

Kunkel³

2002

Abstract.As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. This wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor.

“…Previous work [1,5,8,[13][14][15][16][17][19][20][21][22] studied the effects that speculatively executed memory references have on the performance of out-of-order superscalar processors. These papers yield several conclusions.…”

Section: Introductionmentioning

confidence: 99%

Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

Yilmazer

et al. 2006