xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing

Wang, Xi; Leidel, John D.; Williams, Brody; Ehret, Alan; Mark, Miguel; Kinsy, Michel A.; Chen, Yong

doi:10.1109/ipdps49936.2021.00054

Cited by 9 publications

(4 citation statements)

References 24 publications

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“…Recently, RISC-V ISA has been expanding and penetrating into the high-performance computing (HPC) industry and is expected to be used in applications such as weather forecasting, car crash simulation, material simulation, etc. Current research on the extension of RISC-V in HPC scenarios include global address space extension [8] and remote atomic extension [49]. Wang et al [8] proposed an Extended Base Global Address Space (xBGAS) extension.…”

Section: F High Performance Computingmentioning

confidence: 99%

“…Current research on the extension of RISC-V in HPC scenarios include global address space extension [8] and remote atomic extension [49]. Wang et al [8] proposed an Extended Base Global Address Space (xBGAS) extension. Through the addition of ISA support for remote direct shared memory accesses, the xBGAS extension helps to cut down on the unnecessary software overhead that is associated with internode connections.…”

Section: F High Performance Computingmentioning

confidence: 99%

“…For artificial intelligence applications, works [6] and [7] proposed instruction set extensions for acceleration of deep learning algorithms. A lot of research is also being done on customising RISC-V instruction set extensions for high performance computing [8], graphics computing [9], communication [10], [11], security [12], and so on.…”

Section: Introductionmentioning

confidence: 99%

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RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: F High Performance Computingmentioning

confidence: 99%

Section: F High Performance Computingmentioning

confidence: 99%

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RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…Interestingly enough, when going to 64-bit addresses, the operating system community considered how this vast space could be used [8] and proposed, among others, to access external objects transparently through the network. This idea is currently being pursued with larger address spaces in mind, e.g., [9], although ad-hoc extensions are used rather than going all the way to a flat 128-bit space.…”

Section: B More Than 64-bit Address Initiativesmentioning

confidence: 99%

Fast simulation of future 128-bit architectures

Portas

Pétrot

2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Whether 128-bit architectures will some day hit the market or not is an open question. There is however a trend towards that direction: virtual addresses grew from 34 to 48 bits in 1999 and then to 57 bits in 2019. The impact of a virtually infinite addressable space on software is hard to predict, but it will most likely be major. Simulation tools are therefore needed to support research and experimentation for tooling and software. In this paper, we present the implementation of the 128-bit extension of the RISC-V architecture in the QEMU functional simulator and report first performance evaluations. On our limited set of programs, simulation is slowed down by a factor of at worst 5 compared to 64-bit simulation, making the tool still usable for executing large software codes.

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