xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures

Joven, Jaume; Font-Bach, Oriol; Castells-Rufas, David; Martı́nez, Ricardo; Terés, Lluís; Carrabina, Jordi

doi:10.1109/pdp.2008.24

Cited by 23 publications

(9 citation statements)

References 19 publications

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“…XeNoC [14] is an environment for the automated design of NoC-based systems, starting from an XML configuration file to implementation on Altera FPGAs. It offers both wormhole and deflecting routing, and a wide variety of 2D NoCs, including torus and spidergon.…”

Section: Related Workmentioning

confidence: 99%

The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA

Robino

Öberg

2013

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Future embedded systems will make use of many hundred, configurable or re-configurable, processing elements communicating through a network on chip (NoC), but there is lack of rapid automated design flows bridging the abstraction gap between the models of such systems and their implementation.Designing and programming NoC-based MPSoCs is a complex and error prone activity. However, capturing the design specification at a higher-level of abstraction using models based on models of computation (MoCs) offers a promising way of reducing design flaws at an early stage in the design flow.In this paper, we present the HeartBeat model, a concept for implementing applications based on the synchronous model of computation onto a NoC-based MPSoC platform on FPGA. Furthermore, we show that a platform complying to the constraints imposed by the HeartBeat model has real-time properties.The presented design flow significantly reduces the design time of a real-time embedded system implemented on a NoCbased MPSoC platform, enabling rapid design space exploration through fast prototyping of the solution.

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Section: Related Workmentioning

confidence: 99%

The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA

Robino

Öberg

2013

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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“…As a result, STARSoC generates a bus-based MPSoC platform from a high-level application specification. xENOC [14] is an environment for hardware/software automated design of NoC-based MPSoC architectures. The core of this environment is an EDA tool, called NoCWizard, which can generate RTL Verilog NoCs.…”

Section: Related Workmentioning

confidence: 99%

MppSoCGEN: A Framework for automatic generation of MppSoC Architecture

Kallel¹

2012

IJCSIT

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Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures.

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“…For instance, Joven et al [5] propose the xENOC, which is a framework that allows exploring the design of NoC-based MPSoC architectures. The framework comprises a tool, called NoCWizard, for RTL Verilog NoCs generation, which uses XML file as input.…”

Section: Related Workmentioning

confidence: 99%

“…The architecture provides a number of open-source IP cores such as PEs (Plasma [7], MB-Lite [8], ZPU [9]), a UART, a timer, and a CAN controller connected to a Wishbone bus [10]. Similar to the Joven's approach [5], a XML file is used together with VHDL for describing the architecture. However, no synthesizable NoC is provided.…”

Section: Related Workmentioning

confidence: 99%

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration

Busseuil

Barthe

Almeida

et al. 2011

2011 International Conference on Reconfigurable Computing and FPGAs

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International audienceAs complexity of embedded system increases, configurable hardware is becoming more attractive because it provides a fast and efficient basis for design development. As a consequence, one of the most promising embedded architecture consists in the replication of Processing Elements (PEs)connected through a Network-on-Chip (NoC). Such architectures provide computation parallelism, scalability, and reduced design time thanks to reusability. This paper describes the development of a scalable, distributed memory, open-source NoC-based platform called Open-Scale and itsimplementation into FPGA devices. The main objective of this platform is to provide a complete framework for research development on NoC-based distributed memory MPSoCs

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xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures

Cited by 23 publications

References 19 publications

The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA

The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA

MppSoCGEN: A Framework for automatic generation of MppSoC Architecture

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration

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