The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA

Robino, Francesco; Öberg, Johnny

doi:10.1109/recosoc.2013.6581536

Cited by 7 publications

(3 citation statements)

References 21 publications

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“…Almost all architectural works for improving DVFS management techniques are implemented as part of operating systems (OS-managed scheme). However, novel architectures exploit hardware-assisted mechanisms to manage resources [30][31][32]. DVFS does not limit any of the hardware techniques of SoC designers.…”

Section: Hardware-managed Dvfsmentioning

confidence: 99%

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan

2020

Computers

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Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.

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Section: Hardware-managed Dvfsmentioning

confidence: 99%

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Haririan

2020

Computers

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“…The HeartBeat model in Nostrum NoC [6], is an intermediate platform model bridging the abstraction gap between the synchronous MoC and a NoC-based MPSoC platform. It provides the synchronous communication system and enables the MPSoC to expose the same semantics of the synchronous MoC.…”

Section: A Nostrum Synchronous Nocmentioning

confidence: 99%

Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs

Seyyedi

Mohammadat

Fakih

et al. 2017

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)

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NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. In this presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2x2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantums that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in future work.

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“…The transformation tool takes C-code in the form of equations, and produces a Double-Precision Floating Point implementation of the code, in the form of a VLIW processor. [1][2][3][4][5] However, the double precision operations provided by VHDL-2008 provided by the 1076.3 working group are not efficient enough. The reason is due to that the arithmetic operators used are not pipelined, making them inherently slow after implementation.…”

Section: Introductionmentioning

confidence: 99%

Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite

2014

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Testing HW IP Blocks in multi-core environments is difficult. This paper presents a case study where a SINE/COSINE implementation using Pipelined Double-precision operations is implemented in one node, and results are sent through the NoC to a target node for inspection. The purpose of the experiments are two-fold, a) to study how debugging in a multi-core environment can be done and b) to examine why the original SINE/COSINE implementation is generating wrong results. During the experiments, several testmethods are applied to validate the implementations until the Floating Point implementation are generating correct values. After eliminating all faults in the operations, the SINE/COSINE function still generates some residual algorithmic errors, coming from the way the function was implemented. However, the experiments show that these errors can be eliminated with the help of some simple trigonometric rules.

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The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA

Cited by 7 publications

References 21 publications

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs

Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite

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