XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

“…Another benefit of using a coarse-grained architecture is the reduced configuration data size and hence reduced reconfiguration latency which can allow faster context switching. Because of this apparent advantage, researchers have explored a number of ASIC implementations of coarse-grained reconfigurable architectures (CGRAs) [17], [18], [19], [20], [21], [22], [23], [24], [25]. Some key features that enabled these architectures to address signal processing and high performance computing problems more efficiently include: energy efficiency, ease of programming, fast compilation and reconfiguration.…”

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

“…An alternative approach is loop disserving, described in [32] as applied to the PACT-XPP CGRA, in which the underlying hardware is reconfigured inside loop bodies as many times at each kernel iteration. Loop disserving does not need temporary arrays to store intermediate data, but presents a much higher configuration overhead.…”

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

“…Typically the applications which belong to the application domain of CGRAs are characterized by high data transfer rate between the processor and the memory. Only a few approaches ( [4], [6], [7], [8], and [9]) have been followed to tackle the problem of the limited memory bandwidth in CGRAs for exploiting the hardware parallelism.…”

“…A series of vertical and horizontal buses establish communication among the PEs while for storing the intermediate data values shared memory banks exist on the left and the right side of each array's row. To reduce the number of memory accesses, the compiler [7] only reads one element per iteration and generates shift registers to store the data reuse values when array references inside loops read subsequent element positions.…”