XYZ: Hybrid Network on Chip

Abstract

Network-on-ChipNoC architecture provides a good way to build efficient connections and avoid the limitation of bus-based solution. NoC has emerged as a solution to the problems caused by the shared bus communication approach in Systemon-Chip (SoC) implementation. The problems caused by the shared-busses are generally lack of scalability, clock skew, lack of support for current communication and power consumption. The communication requirement of this paradigm is affected by architecture parameters such as the topology, routing, buffer size etc. In this paper, we propose a new approach consisting of an XYZ hybrid Network-on-Chip NoC. This architecture takes on the advantages of the scalable bandwidth of the regular mesh topology and the low latency characteristics of the bus-based networks. We have chosen the store and forwarding switching as switching methods for packets because of the parallel nature of the architecture. We describe in detail the new proposed architecture to get a low latency and give the hardware simulation.