Network-on-ChipNoC architecture provides a good way to build efficient connections and avoid the limitation of bus-based solution. NoC has emerged as a solution to the problems caused by the shared bus communication approach in Systemon-Chip (SoC) implementation. The problems caused by the shared-busses are generally lack of scalability, clock skew, lack of support for current communication and power consumption. The communication requirement of this paradigm is affected by architecture parameters such as the topology, routing, buffer size etc. In this paper, we propose a new approach consisting of an XYZ hybrid Network-on-Chip NoC. This architecture takes on the advantages of the scalable bandwidth of the regular mesh topology and the low latency characteristics of the bus-based networks. We have chosen the store and forwarding switching as switching methods for packets because of the parallel nature of the architecture. We describe in detail the new proposed architecture to get a low latency and give the hardware simulation.

Abstract-Many fault tolerance techniques have been proposed in Network on Chip to cope with defects during fabrication or faults during product lifetime. Fault tolerance routing algorithm provide reliable mechanisms for continue delivering their services in spite of defective nodes due to the presence of permanent and/or transient faults throughout their lifetime implementation. This paper presents a new approach in the domain of fault-tolerant NoC with two main contributions. Firstly, we consider a unified fault model that include transient faults, permanent faults and congestion considered as a fault. Secondly, we present a new architecture based on sub-nets and give an overview of the associated test and (re)routing algorithm. The main result of this paper, is a new routing algorithm called Collaborative Routing Algorithm for Fault Tolerance in Network on Chip (CRAFT-NoC). We compare our approach with ACO-FAR that considers as well congestion and permanent faults. Our simulation results show significant improvements in terms of both latency and reliability.

Abstract:The need for high performance, available and reliable embedded systems has made computing systems increasingly complex. Formal methods have the ability to produce critical systems for large industrial projects, and this by creating an original mathematical model that can be formally refined in levels until the final refinement which contains enough of details for an implementation. This work is a first step of VHDL code generation process, it represents how to elaborate formally an embedded system using Abstract data type in a form of theories (NoC, WNoC, colored graph, VHDL) and how to ensure in systematic way all the details and complexity of this system using operators of refinement (Create, Rename, Restrict, Enrich)that are recently proposed for the Event-B method. All the theories are deployed, discharged and used in Event-B models to represent and enhance the performance of this self-organization reliability solution for the wireless sensors network of NoC-based system. This paper summerize the fruit of using new proposed approach for the Event-B formal method that persist the NoC-based ditributed system instead of consuming more than 70% of realization time with any analytic method.