Yet another silicon compiler

Silicon compilation based on a data-flow paradigm

“…In this section, we will discuss the features of a data-flow language that are used by the YASC silicon compiler [6]. In order to explain the various constructs in the language, we will consider an example system specification.…”

“…The first major task is logic synthesis, in which a logic-level description of the initial YASC specification is obtained. This level of design description can be cast in a well-defined lan guage of its own, known as Boolean Intermediate Form, or BIF [6]. Then, the BIF code can be used to generate silicon layout through one or more paths, as shown in the same figure.…”

“…Then, the BIF code can be used to generate silicon layout through one or more paths, as shown in the same figure. Here we illustrate three possible compilation paths; PLAs can be generated through tools such as EQNTOTT [10] and MKPLA [11], while random logic can be generated through the use of symbolic cell matrix generators [6] or SLAP [12]. As illustrated, some simple code-converters can be constructed to obtain the proper input format for each tool.…”