Yield-Driven, False-Path-Aware Clock Skew Scheduling

Abstract

SEMICONDUCTOR TECHNOLOGY ADVANCES have enabled designers to integrate more functionality in a single chip. As design complexity increases, many new design techniques are developed to optimize chip area and power consumption, as well as performance. Traditionally, yield improvement has been achieved through process improvement. However, in deep-submicron technologies, process variations are difficult to control. As a result, many design decisions significantly affect yield. Therefore, designers should consider yield-related issues during the design phase.Timing failure is a major cause of yield loss for highperformance circuits. Although designers have used clock skew scheduling to increase operation frequency, there is little research addressing its impact on yield. We propose a novel clock-skew-scheduling scheme that improves yield without sacrificing performance. The scheme achieves this by combining accurate path delay information using our efficient sensitizable-critical-path search algorithm and a proportional slack distribution heuristic. Our experimental results show substantial yield improvement in many of the ISCAS89 and ITC99 benchmark circuits, and in one case improvement is as high as 50%. Existing methodsIn a zero-skew design, the circuit's longest path delay limits the shortest clock period. Properly assigning clock arrival times to each sequential element or introducing clock skew at various storage elements can help operate a circuit at a higher clock frequency.1,2 Because timing failure is the major cause of yield loss, proper clock skew assignment for performance and yield is extremely important. Previous works attempted to reduce susceptibility to delay defects caused by process variations by finding a clock skew schedule that minimizes the number of paths with small slack.3,4 However, as we show in this article, these approaches might not always improve yield, and the researchers did not verify their results with a yield model. Clock period optimizationTo increase operation frequency, designers have adopted techniques such as circuit retiming and pipelining to balance path delays in different parts of the circuit. Because path delays usually cannot be perfectly balanced, the application of clock skew scheduling can further optimize the clock period.1-3 Figure 1a shows an example circuit with three flip-flops. The maximum and minimum path delays between FF i and FF j are D ij and d ij , respectively. CP is the clock period, and T setup and T hold are the FF setup and hold times. Without clock skew scheduling and with zero slack, this design will have CP = max{D ij } + T setup . For this example, the value of CP is 4 where T setup = T hold = 0. However, to determine the optimal clock period with clock skew scheduling, we first define the clock arrival time to FF i as T i and the clock skew between FF i and FF j as s ij = T i -T j . By absorbing the FF delays as part of the path delays, we can write the hold time and setup time constraints as Yield-Driven, False-Path-Aware Clock Skew Scheduling ...