Yield-enhanced routing for high-performance VLSI designs

Venkataraman, A.; Chen, Howard H.; Koren, Israel

doi:10.1117/12.284707

Cited by 8 publications

(2 citation statements)

References 13 publications

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“…An algorithm for layer assignment in a two-layer routing, which reduces the critical area due to via defects and open-and short-circuit defects was described in [8]. Yield-enhanced routing was recently presented in [101] for a gridless channel routing, which allows a more flexible positioning of the horizontal wire segments.…”

Section: ) Compaction Strategies For Yield Enhancementmentioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

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Section: ) Compaction Strategies For Yield Enhancementmentioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

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“…Because the critical area is directly related to the layout of the design, many schemes have been developed for reducing the critical area at the physical design level, such as during placement [3], routing [4], compaction [5], and cell library preparation [6]. Usually, the yield is dealt with as a secondary optimization goal.…”

Section: Introductionmentioning

confidence: 99%

An ILP formulation for yield-driven architectural synthesis

Koren

Ciesielski

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

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Data flow graph dominant designs, such as communication video and audio applications, are common in today's IC industry. In these designs, the datapath resources (e.g., adders, multipliers) count more than 90% in area. Different datapath resources have very different properties in terms of area, delay, power and yield. Considering yield during system level design can result in significant benefits. A Mixed Integer Linear Programming (MILP) formulation for yield-aware architectural synthesis is presented in this paper. The proposed approach attempts to maximize the yield of the design while satisfying other constraints like area and delay. Through experiments on several benchmarks, we show that incorporating the yield as an objective during architectural synthesis can significantly improve the yield compared to conventional methods. Transistor sizing at the circuit level can also be incorporated in our method to further improve the yield.

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Wire planning for performance and yield enhancement

Ouyang¹,

Ryu²,

Heineken³

et al.

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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In this papec a wire planning strategy at the layout stage is proposed. The strategy addresses deep submicron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitiviiy to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.

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Yield-enhanced routing for high-performance VLSI designs

Cited by 8 publications

References 13 publications

Defect tolerance in VLSI circuits: techniques and yield analysis

Defect tolerance in VLSI circuits: techniques and yield analysis

An ILP formulation for yield-driven architectural synthesis

Wire planning for performance and yield enhancement

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