Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements

Narasimham, Jaganathan; Nakajima, Kazuo; Rim, C.S.; Dahbura, Anton

doi:10.1109/43.298034

Cited by 41 publications

(15 citation statements)

References 17 publications

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“…One is simply to note the locations of faulty cells and reroute the user's circuit to avoid them using spares or other unused cells instead. This has been proposed for use in programmable gate arrays designed to be programmed at the factory, and, potentially, requires a different routing for every chip to which the user's circuit is mapped [18], [20]. It has also been proposed for (primarily) logic cell faults in FPGAs in [12], [19], and, specifically, for wiring faults in [21].…”

Section: Existing Fault Tolerance Methodsmentioning

confidence: 99%

“…Our proposed methods of fault tolerance require neither the factory nor the user to generate new routing maps to reconfigure around faulty cells or wiring, as is required by [12], [18], [19], [20], [21], so no additional time is spent with routing tools each time a chip is to be programmed. Instead, the original configuration data can be reused.…”

Section: Proposed Fault-tolerant Methodsmentioning

confidence: 99%

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Methodologies for tolerating cell and interconnect faults in FPGAs

Hanchek

Dutt

1998

IEEE Trans. Comput.

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The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational faults. Thus, there is a critical need for fault tolerance and reconfiguration techniques for FPGAs to increase chip yields (with factory reconfiguration) and/or system reliability (with field reconfiguration). We first propose techniques utilizing the principle of node-covering to tolerate logic or cell faults in SRAM-based FPGAs. A routing discipline is developed that allows each cell to cover-to be able to replace-its neighbor in a row. Techniques are also proposed for tolerating wiring faults by means of replacement with spare portions. The replaceable portions can be individual segments, or else sets of segments, called "grids." Fault detection in the FPGAs is accomplished by separate testing, either at the factory or by the user. If reconfiguration around faulty cells and wiring is performed at the factory (with laser-burned fuses, for example), it is completely transparent to the user. In other words, user configuration data loaded into the SRAM remains the same, independent of whether the chip is defect-free or whether it has been reconfigured around defective cells or wiring-a major advantage for hardware vendors who design and sell FPGA-based logic (e.g., glue logic in microcontrollers, video cards, DSP cards) in production-scale quantities. Compared to other techniques for fault tolerance in FPGAs, our methods are shown to provide significantly greater yield improvement, and a 35 percent non-FT chip yield for a 16 ¥ 16 FPGA is more than doubled.

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Section: Existing Fault Tolerance Methodsmentioning

confidence: 99%

Section: Proposed Fault-tolerant Methodsmentioning

confidence: 99%

Methodologies for tolerating cell and interconnect faults in FPGAs

Hanchek

Dutt

1998

IEEE Trans. Comput.

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“…Like SRAMs fault tolerance methods, the faulty column in the PLB is eliminated and all operations of the columns between the faulty one and the spare are shifted using the spare column algorithm. Narasimhan et al (1991;1994), the authors developed a pebble shift method for fault tolerance in FPGAs. Their methods are based on using unused resources, which is used in fault tolerance.…”

Section: Related Researchmentioning

confidence: 99%

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Krishna¹

2014

Journal of Computer Science

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FPGA is a device that contains a matrix of reconfigurable gate arrays that can implement different complex functions and also vary structurally. In this study, a novel method of reconfigurable circuit switching action is done with the help of a controller. BPSK Modulation application is chosen to demonstrate the reconfigurable action. When an event occurs the context/core switching is done at both input and output and also preserving the structural and functional relationship. The reconfiguration ability of FPGA with an embedded core performing the switching in real time is the focus of this study. A controller running on Linux platform is used along with the FPGA core. In this study, we propose a real time approach for reconfiguring evolved circuits using controller. It has an adaptive hardware that can continuously change in response to the input data and there by perform reconfiguration. Here the reconfiguration process is achieved by using a real time controller which gives a command to the FPGA core (ALTERA (Cypress processor)) for reconfiguration.

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“…To minimise the impact on timing and routing in the area around the fault, pebble shifting is used [45] [46]. In [32] and [33], pebble shifting is used in combination with cluster reconfiguration.…”

Section: 22mentioning

confidence: 99%

Fault tolerant methods for reliability in FPGAs

Stott

Sedcole

Cheung

2008

2008 International Conference on Field Programmable Logic and Applications

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Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this field. All methods and schemes are qualitatively compared and some particularly promising approaches highlighted.

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Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements

Cited by 41 publications

References 17 publications

Methodologies for tolerating cell and interconnect faults in FPGAs

Methodologies for tolerating cell and interconnect faults in FPGAs

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Fault tolerant methods for reliability in FPGAs

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