Yield evaluation methods of SRAM arrays: a comparative study

Ottavi, Marco; Schiano, L.; Wang, X.; Kim, Y.B.; Meyer, F.J.; Lombardi, Fabrizio

doi:10.1109/imtc.2004.1351355

Cited by 3 publications

(1 citation statement)

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“…Solution must also be independent of factors like repair strategy (hard repair / configurable repair etc. [3]), memory types, and redundancy structures [4] etc.…”

Section: Introductionmentioning

confidence: 99%

Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost

Garg

Dubey

2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increase. Laser Fuses and Anti Fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, we present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio.

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“…Solution must also be independent of factors like repair strategy (hard repair / configurable repair etc. [3]), memory types, and redundancy structures [4] etc.…”

Section: Introductionmentioning

confidence: 99%