Yield Learning with Layout-aware Advanced Scan Diagnosis

Abstract

Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.

Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis

“…When seeing yield challenges during manufacturing test, volume failure data logs (6) are collected by the ATE for the targeted lots and wafers. Design image including netlist and layout data (LEF/DEF), test patterns, and failure data are used to perform volume layout-aware scan diagnosis (7,8). The layout-aware diagnosis analyzes the net topology for the suspect segments and eliminates false bridges and unjustified opens.…”