Yield, Power and Performance Optimization for Low Power Clock Network under Parametric Variations in Nanometer Scale Design

Abstract

Advancing in the nanometer regime, parametric variations has made yield a critical parameter to be included right in the beginning of the design process. Low power circuits have to be designed keeping in mind power consumption, minimum performance levels and yield and find the best compromise between all three. Statistical techniques, Monte Carlo Analysis, using log-normal model has been used to study the effect of parametric variations in leakage dominant 65 nm clock network design. Power supply (Vdd) and threshold voltage (Vth) scaling along with length and device sizing optimization is used to achieve best compromise among power consumption, delay and yield depending on the target application. General guidelines based on final application are given.

Pulse width degradation in 45nm ASIC design due to global and environmental variations

“…Clock trees have large path lengths spread over the whole die passing through different power domains making them highly sensitive to such variations. Most of the studies on the impact of PVT variations concentrate on either skew or insertion delay [4]. However, we have restricted the analysis to pulse width with an aim to formulate optimization guidelines.…”