Yield-preferred via insertion based on novel geotopological technology

Luo, Fangyi; Jia, None Yongbo; Dai, Wayne Wei-Ming

doi:10.1145/1118299.1118469

Cited by 37 publications

(22 citation statements)

References 10 publications

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“…We name the modified conflict graph construction algorithm as IGCA. 4 . For GCA, the R-trees for metal layers m and m+1 will consist of all layout objects on the corresponding layers, as shown in Fig.…”

Section: A Speed-up Methods For Conflict Graph Constructionmentioning

confidence: 99%

“…The tools EYE/PEYE [5] consider redundant via insertion in the post-routing stage but the details of how they do redundant via insertion are not described. [13] and [4] also consider redundant via insertion in the post-routing stage. In [4], the single vias of a design are considered one by one to perform redundant via addition, and therefore the solution may just be locally optimal.…”

Section: Metal Layer M+1mentioning

confidence: 99%

“…[13] and [4] also consider redundant via insertion in the post-routing stage. In [4], the single vias of a design are considered one by one to perform redundant via addition, and therefore the solution may just be locally optimal. Besides, since the approach will change the routing result of the timing noncritical nets, it may also induce timing violations even if designers keep the timing critical nets unchanged.…”

Section: Metal Layer M+1mentioning

confidence: 99%

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Post-routing redundant via insertion and line end extension with via density consideration

Lee¹,

Wang²,

Chao³

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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-Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. However, if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design. In this paper, we first study the problem of redundant via insertion, and present two methods to accelerate a state-ofthe-art approach (which is based on a maximum independent set (MIS) formulation) to solve it. We then consider the problem of simultaneous redundant via insertion and line end extension. We formulate the problem as a maximum weighted independent set (MWIS) problem and modify the accelerated MIS-based approach to solve it. Lastly, we investigate the problem of simultaneous redundant via insertion and line end extension subject to the maximum via density rule, and present a two-stage approach for it. In the first stage, we ignore the maximum via density rule, and enhance the MWIS-based approach to find the set of regions which violate the maximum via density rule after performing simultaneous redundant via insertion and line end extension. In the second stage, excess redundant vias are removed from those violating regions such that after the removal, the maximum via density rule is met while the total amount of redundant vias removed is minimized. This density-aware redundant via removal problem is formulated as a set of zero-one integer linear programming (0-1 ILP) problems each of which can be solved independently without sacrificing the optimality. The superiorities of our approaches are all demonstrated through promising experimental results.

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Section: A Speed-up Methods For Conflict Graph Constructionmentioning

confidence: 99%

Section: Metal Layer M+1mentioning

confidence: 99%

Section: Metal Layer M+1mentioning

confidence: 99%

See 1 more Smart Citation

Post-routing redundant via insertion and line end extension with via density consideration

Lee¹,

Wang²,

Chao³

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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“…Therefore, redundant via [31], [41] and redundant wire [5], [26] insertions have been proposed to improve manufacturing yield. However, traditional redundant via insertion is not compatible with unidirectional routing style as shown in Fig.…”

Section: Redundant Local-loop Insertionmentioning

confidence: 99%

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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“…In [41], the redundant via insertion is formulated as a maximum independent set (MIS) problem, and solved by heuristic approach. Different redundant via insertion based on geotopography information is proposed in [42] where a redundant via is tried for each original via in greedy manner. However, as excessive number of vias can even worsen yield, redundant via insertion under via density constraint is required which is addressed in [43] based on the integer linear programming.…”

Section: ) Redundant-via Aware Routingmentioning

confidence: 99%

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

Pan

Cho

2008

2008 Asia and South Pacific Design Automation Conference

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Abstract-Nanometer IC designs are increasingly challenged by manufacturing closure, i.e., being fabricated with high product yield, mainly due to aggressive technology scaling and increasing process/environmental variations. Realizing the criticality of addressing manufacturability for higher yield and tolerance to variations during design, there has been a surge of research activities recently from both academia and industry. In this paper, we will survey the key activities in synergistic physical synthesis and shed lights on some of the future research directions.

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Yield-preferred via insertion based on novel geotopological technology

Cited by 37 publications

References 10 publications

Post-routing redundant via insertion and line end extension with via density consideration

Post-routing redundant via insertion and line end extension with via density consideration

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

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