Yield Simulation for Integrated Circuits

Walker, D.M.H.

doi:10.1007/978-1-4757-1931-4

Cited by 123 publications

(27 citation statements)

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“…The last four colums of the chart correspond to different values of p using the heuristic in Equation (12). Table 1 confirms the results predicted in the previous Section: assuming yield follows a Poisson model, p = N leads to best results for effective yield.…”

Section: Technology Mapping For Manufacturabilitysupporting

confidence: 80%

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Synthesis for manufacturability: a sanity check

Nardi¹,

Sangiovanni-Vincentelli²

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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Section: Technology Mapping For Manufacturabilitysupporting

confidence: 80%

“…[8,12]) on how to derive a model to accurately predict yield with clustered defect distributions. Nevertheless, our research is aimed at analyzing how synthesis for manufacturability can lower manufacturing cost rather than doing an exact yield prediction.…”

Section: Introductionmentioning

confidence: 99%

Synthesis for manufacturability: a sanity check

Nardi¹,

Sangiovanni-Vincentelli²

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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“…Since the benchmarks lack detailed pin locations, one to five pins for each global routing cell on each wire are randomly generated to define the preferred position of each wire (M i ). A Monte Carlo simulation [41] with 10 000 random defects based on (1) is performed to estimate yield loss. Also, these random defects are assumed to be uniformly distributed on the chip for fair estimation.…”

Section: Resultsmentioning

confidence: 99%

Track Routing and Optimization for Yield

Cho

Xiang

Puri

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wire ordering, sizing, and spacing, track routing can play a key role in effective wire planning for yield optimization. However, a straightforward formulation of yield-driven track routing can be shown to be integer nonlinear programming, which is a nondeterministic polynomial-time complete problem. TROY overcomes the computational complexity by combining two effective techniques, i.e., the minimum Hamiltonian path (MHP) from graph theory and the second-order cone programming (SOCP) from mathematical optimization. First, TROY performs wire ordering to minimize the critical area for short defects by finding an MHP. Then, TROY carries out optimal wire sizing/spacing through SOCP optimization based on the given wire order. Since the SOCP can be optimally solved in near linear time, TROY efficiently achieves globally optimal wire sizing/spacing for the minimal POF.Index Terms-Minimum Hamiltonian path (MHP), physical design, random defects, second-order cone programming (SOCP), track routing, yield.

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“…For instance, in the context of semiconductor wafer fabrication, the first stage corresponds to wafer probe, an important step that involves computer-controlled automatic testing; while the second stage involves a more routine, final inspection; refer to Lee [10]; also Walker [17]. Other related recent studies include: Cassandras [5], on "yield learning," focusing on threshold control policies; and Yao and Zheng [18], on process control using Markov decision programming, and also focusing on the optimality of threshold policies.…”

Section: Introductionmentioning

confidence: 99%

Coordinated quality control in a two-stage system

Yao

Zheng

1999

IEEE Trans. Automat. Contr.

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We study a quality control problem in a two-stage system. We assume that at each stage units are processed in batches, and the rates are random variables with known distributions. Final products are supplied to customers under warranties or service contracts, with penalty costs associated with defective units. Our focus is on coordinating the inspection procedures at the two stages. Using a stochastic dynamic programming approach, we show that the optimal policy at stage 1 is characterized by a sequence of thresholds, and at stage 2, by a priority structure, as well as a threshold structure. The key to optimality is a so-called K-submodularity property, which is a strengthening of the usual notion of submodularity.

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Yield Simulation for Integrated Circuits

Cited by 123 publications

References 0 publications

Synthesis for manufacturability: a sanity check

Synthesis for manufacturability: a sanity check

Track Routing and Optimization for Yield

Coordinated quality control in a two-stage system

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