Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

Spiesshoefer, S.; Schaper, L.W.; Burkett, S. L.; Vangara, G.; Rahman, Zia Ur; Arunasalam, Parthiban

doi:10.1109/ectc.2004.1319380

Cited by 37 publications

(16 citation statements)

References 2 publications

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“…Wafer stacking relies on Through-Silicon Vias (TSVs) [14] for vertical connectivity, guaranteeing low parasitics (i.e. low power and propagation delay) and, if needed, extremely high densities of vertical wires (i.e.…”

Section: Physical Level Modeling and Analysis Of Tsv Fault Impactmentioning

confidence: 99%

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

Loi¹,

Mitra²,

Lee³

et al. 2008

2008 IEEE/ACM International Conference on Computer-Aided Design

151

107

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Abstract-Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area-and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defecttolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of VLSI design and test flows.

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Section: Physical Level Modeling and Analysis Of Tsv Fault Impactmentioning

confidence: 99%

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

Loi¹,

Mitra²,

Lee³

et al. 2008

2008 IEEE/ACM International Conference on Computer-Aided Design

151

107

View full text Add to dashboard Cite

show abstract

“…An approach to high-density TSV interconnection using a variety of CMOS-compatible fabrication steps (such as CVD tungsten and polysilicon, ECD copper, and solder micro-bumps) is presented by Knickerbocker et al in References 86 and 87. Spiesshoefer et al [88,89] have discussed the formation of TSVs using RIE. While the need for high-density interconnection drives the work to produce HAR vias, the need for void-free filling requires a sidewall with some tapering.…”

Section: Through-silicon Viasmentioning

confidence: 99%

Three‐Dimensional (3D) Integration

McMahon

Gutmann

2007

Microelectronic Applications of Chemical Mechanical Planarization

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Three-dimensional (3D) integration with interstrata vias has the potential of improving system performance while providing a platform for heterogeneous integration. Performance improvement in 3D integrated circuits (ICs) is mainly due to the reduction of interconnect length, which decreases interconnect delay and power consumption [1,2]. Small form factor is achieved in 3D ICs due to the stacking of active device layers one on top the other. A path for heterogeneous integration is realized if this stacking is done in a fashion that is back-end-of-line (BEOL) compatible, because interconnecting devices using fully fabricated wafers can reduce process incompatibilities.Approaches to 3D integration are often divided into die-level approaches and wafer-level approaches. Most often, the heterogeneous integration and small form factor advantages are obtained with die-level approaches; in addition, high performance and low manufacturing cost can be achieved with wafer-level approaches.CMP has permeated many aspects of IC processing but is particularly a dominant factor in BEOL interconnection. Copper damascene patterning has become the standard methodology for building a large number of interconnect layers in the vast majority of high-performance ICs. In 3D ICs, CMP is also critical in backside thinning, surface roughness reduction, and, in particular, feature topography control. Topography mitigation can particularly be a critical Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li

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“…In this paper we focus on wafer stacking approaches, as one of the most promising avenues for the implementation of high-performance yet inexpensive (multiple 3D chips can be processed in a single pass) three-dimensional ICs. Wafer stacking relies on Through-Silicon Vias (TSVs) [7] for vertical connectivity, guaranteeing low parasitics (i.e. low latency and power) and, if needed, extremely high densities of vertical wires (i.e.…”

Section: Previous Work a Vertical Stackingmentioning

confidence: 99%

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Loi

Angiolini

Benini

2007

Proceedings of the Second International Conference on Nano-Networks

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Abstract-Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networkson-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of ThroughSilicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.

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Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

Cited by 37 publications

References 2 publications

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

Three‐Dimensional (3D) Integration

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

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