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Benini, Luca; Bruni, D.; Chinosi, M.; Silvano, Cristina; Zaccaria, Vittorio; Zafalon, R.

doi:10.1023/a:1019722105713

Cited by 10 publications

(1 citation statement)

References 25 publications

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“…Here, the power consumed by an instruction is dependent on three parametersopcode/operands of the instruction, other instructions in the bundle, and the pipeline/circuit state. Benini et al (2001) adopt a simpler approach for VLIW processors. They pass the instruction trace to an architectural power simulator that is calibrated with RTL models.…”

Section: Data Independent Approachesmentioning

confidence: 99%

Processor power estimation techniques: a survey

Sultan¹,

Ananthanarayanan²,

Sarangi³

2014

IJHPSA

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Since the end of the nineties, power dissipation has been regarded as a first order design constraint in processors. Increased power dissipation along with the resultant rise in die temperature is considered as the single largest bottleneck for increasing processor frequency and complexity. Consequently, it is very important from both a technical as well as commercial perspective to accurately estimate processor power such that designers can tailor their architecture, software and systems to minimize power consumption. In this paper, we provide a survey of most of the processor specific power estimation techniques proposed after the mid nineties. In specific, we look at estimating power both at design time as well as runtime. The former approach is more suitable for early stage architectural exploration, and the latter approach is more germane to creating power efficient application software. We broadly focus on estimating power using system level models, architectural simulation, hardware performance counters, on-chip temperature profiles, and program execution profiles. We showcase a broad range of methods for power estimation using simulators, compilers, profilers, and sophisticated mathematical analysis routines.

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Section: Data Independent Approachesmentioning

confidence: 99%