2012
DOI: 10.1143/jjap.51.04dd02
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Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Abstract: The thermal response of a semi-infinite medium in air, irradiated by laser light in a cylindrical geometry, cannot accurately be approximated by single radial and axial time constants for heat conduction. This report presents an analytical analysis of heat conduction where the thermal response is expressed in terms of distributions over radial and axial time constants. The source term for heat production is written as the product of a Gaussian shaped radial term and an exponentially shaped axial term. The two … Show more

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Cited by 5 publications
(2 citation statements)
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“…Although a standard CMOS process cannot fabricate a commonly used flash memory element with a double-gate structure, several attempts have been made to implement CMOS-processcompatible non-volatile memory elements, as summarized in Table 1. These can be classified into three types: anti-fuse memory elements [8]; CHEI-based memory elements [9], [10], [11], [12], [13], [14], [15]; and FN-tunneling-based memory elements [7].…”
Section: Cmos-technology-compatible Non-volatile Memorymentioning
confidence: 99%
See 1 more Smart Citation
“…Although a standard CMOS process cannot fabricate a commonly used flash memory element with a double-gate structure, several attempts have been made to implement CMOS-processcompatible non-volatile memory elements, as summarized in Table 1. These can be classified into three types: anti-fuse memory elements [8]; CHEI-based memory elements [9], [10], [11], [12], [13], [14], [15]; and FN-tunneling-based memory elements [7].…”
Section: Cmos-technology-compatible Non-volatile Memorymentioning
confidence: 99%
“…CHEI is widely used in writing flash memories, and various studies have attempted to apply it to CMOS-process-compatible non-volatile memory elements [9], [10], [11], [12], [13], [14], [15]. References [10], [11], and [13] used a MIM capacitor, MOS capacitors, and a contact coupling gate, respectively, to form a floating gate, while the others trapped carriers in the gate oxide [12], [14], [15], or SiN sidewalls [9]. References [9], [15], and [11] successfully stored two-bit, three-bit, and analog data, respectively, in one memory cell.…”
Section: Chei-based Memory Elementmentioning
confidence: 99%