ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays

Abstract

Multi-Electrode Arrays and High-Density Multi-Electrode Arrays of sensors are a key instrument in neuroscience research. Such devices are evolving to provide ever-increasing temporal and spatial resolution, paving the way to unprecedented results when it comes to understanding the behaviour of neuronal networks and interacting with them. However, in some experimental cases, in-place lowlatency processing of the sensor data acquired by the arrays is required. This poses the need for highperformance embedded computing platforms capable of processing in real-time the stream of samples produced by the acquisition front-end to extract higher-level information. Previous work has demonstrated that Field-Programmable Gate Array and All-Programmable System-On-Chip devices are suitable target technology for the implementation of real-time processors of High-Density Multi-Electrode Arrays data. However, approaches available in literature can process a limited number of channels or are designed to execute only the first steps of the neural signal processing chain. In this work, we propose an All-Programmable System-On-Chip based implementation capable of sorting neural spikes acquired by the sensors, to associate the shape of each spike to a specific firing neuron. Our system, implemented on a Xilinx Z7020 All-Programmable System-On-Chip is capable of executing on-line spike sorting up to 5500 acquisition channels, 43x more than state-of-the-art alternatives, supporting 18KHz acquisition frequency. We present an experimental study on a commonly used reference dataset, using on-line refinement of the sorting clusters to improve accuracy up to 82%, with only 4% degradation with respect to off-line analysis. INDEX TERMS Field programmable gate arrays, Signal processing, Neural engineering, APSoC, HDMEA, Spike sorting.

On-FPGA Spiking Neural Networks for End-to-End Neural Decoding

“…A uC is used in [22] for implementing a low-cost neural interface solution for EEGbased neural decoding during a hand open/close/idle state classification task using a Bayesian classifier. Although several hardware solutions have been proposed for intracortical neural signal processing, most of them stop at the spike detection phase [25] or at the spike sorting phase [26]. Similarly, among numerous existing SNN accelerators, some are oriented to understand the brain functionalities, exploiting either FPGA-based prototypes [27], or higherend emulators such as SpiNNaker [28].…”

Low-latency extracellular spike assignment for high-density electrodes at single-neuron resolution

“…However, FPGA programming or chip design is a highly involved process requiring specialized skills. So far, on-chip spike sorting systems have only used single-channel waveform features [27][28][29][30][31][32] or been implemented with a simplified multichannel waveform clustering algorithm 33,34 . Evidence underscores the need for sophisticated algorithms [35][36][37] or even manual curation 38 to separate multichannel spike waveform features from individual neurons and from noise.…”

“…The design delivers flexibility speed, assigning single-neuron identities to all detected single-spikes with 1-millisecond latency across 160 channels 39 , and has recently been deployed in online experiments 40 . Unlike prior reports [27][28][29][30][31][32][33][34] , our platform accommodates multichannel spike waveforms and is compatible with tetrodes and silicon probes, while enabling modern clustering algorithms and manual curation for crafting accurate spike-sorted models. To abstract the hardware complexities, we provide a backend Application Programming Interface (API) and frontend modular Graphical User Interface (GUI) components for intuitive data visualization, data management, model curation, and FPGA-NSP status control.…”

A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA

“…These kinds of tools can help the investigation of how neurons interact with each other, even though more and more often they are also exploited to address completely different problems, such as neuromorphic computing [3]. New generation High-Density Multielectrode Array, scaled from hundreds to thousands of recording sites [4], pushing for the development of signal processing systems capable of sorting order of magnitude more neural data in real-time than in the past [5], and artificial neural networks capable to keep up and process the incoming data. This translates into an imminent demand for bigger and more-connected neural networks.…”