Verification of a computer that implements a new architecture is especially difficult since no approved functional test cases are available. The logic design of the IBM RiSe System/6000 TII was verified mainly by a specially developed random test program generator (RTPG), which was used from the early stages of the design until Its successful completion. APL was chosen for the RiSe System/6000 RTPG implementation after considering the suitability of this programming language for modeling computer architectures, the very tight schedule, and the highly changeable environment in which RTPG would operate.T he ultimate goal of design verification is to ensure equivalence between a design and its functional specification. Strictly speaking, we can say that this goal can be achieved by exhaustive simulation or formal proof of correctness. The exhaustive simulation, in which all possible combinations of all inputs and memory elements of the design should be applied, can be done only for very small designs. Also, the state of the art of the formal techniques and the complexity of designs and specifications, usually written in English, do not allow utilization of the formal techniques in most industrial applications. 1 Despite significant progress

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