A 25 MHz Viterbi FEC codec

Kerr, R.; Dehesh, H.; Bar-David, A.; Werner, D.

doi:10.1109/cicc.1990.124729

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…We use the terminology and results derived by Viterbi and Omura in [20]. The truncation error probability is used to determine an The conventional VA with best state decoding for time instant k can hence be represented as (6) since the multiplication with (1, . .…”

Section: IVmentioning

confidence: 99%

A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation

Dawid

Fettweis

Meyr

1996

IEEE Trans. VLSI Syst.

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At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the "minimized method" (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a Conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 p CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

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Section: IVmentioning

confidence: 99%

A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation

Dawid

Fettweis

Meyr

1996

IEEE Trans. VLSI Syst.

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“…This should suffice as margin for the uncertainty of the design completion. Including a pad ring in the estimate 1ea.ds to a die size of 64mm2 ( l p m technology), whereas the decoder for the reference code [12] required 67mm2 in 0.7pm technology. This shows that the proposed scheme is indeed competitive.…”

Section: Unit(s)mentioning

confidence: 99%

“…But even with a less precise result we would have been able to choose from the parameter sets of Table 6 which would greatly reduce the parameter search space. To compare we included a performance graph of a commercial decoder for the reference code (taken from [12]). An honest comparison of the single coder scheme versus the concatenated scheme requires an actual area result.…”

Section: Unit(s)mentioning

confidence: 99%

Systematic design optimization of a competitive soft-concatenated decoding system

Joeressen

Schneider

Meyr

Proceedings of IEEE Workshop on VLSI Signal Processing

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Tel: +4 9-24 I -$07632, email: joeresse8ert. rwth-aachen. deDue to the advances in VLSI technology complete digital communication systems can today be implemented on single application specific VLSI circuits. The optimum choice of implementation parameters, such as signal wordlengths, is a critical design task since poor parameter choices can lead to costly designs. On the other hand, the high number of parameters to be selected span a large search space that is very difficult to handle. We present a new systematic approach to parameter selection in this paper and apply this approach to the design optimization of a decoding system for a concatenated coding scheme. Two convolutional codes are concatenated and both are decoded by soft decision decoding. This is facilitated by means of soft output decoding of the inner code. The performance of the scheme is better than that of the well known standard code with 64 states for moderate BER at equivalent implementation cost. The proposed coding scheme is thus an attractive alternative whenever high bit error rate performance is a prerequisite, e.g. for digital HDTV transmission.

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