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Abstract. Positive Feedback Adiabatic Logic (PFAL) shows the lowest energy dissipation among adiabatic logic families based on cross-coupled transistors, due to the reduction of both adiabatic and non-adiabatic losses. The dissipation primarily depends on the resistance of the charging path, which consists of a single p-channel MOSFET during the recovery phase. In this paper, a new logic family called Improved PFAL (IPFAL) is proposed, where all n-and pchannel devices are swapped so that the charge can be recovered through an n-channel MOSFET. This allows to decrease the resistance of the charging path up to a factor of 2, and it enables a significant reduction of the energy dissipation. Simulations based on a 0.13µm CMOS process confirm the improvements in terms of power consumption over a large frequency range. However, the same simple design rule, which enables in PFAL an additional reduction of the dissipation by optimal transistor sizing, does not apply to IPFAL. Therefore, the influence of several sources of dissipation for a generic IPFAL gate is illustrated and discussed, in order to lower the power consumption and achieve better performance.

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Abstract. Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage.By means of adder structures designed for a 0.13 µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

Absfrazl . A large number of adiabatic families has beenproposed, but there exist only few partial comparisons and no methodical investigations of the robustness of such circuits. Using a 4-bit adder as a reference circuit we compare different adiabatic logic families with respect to energy consumption, area occupation and frequency range. Significant differences among various adiabatic implementations are found and a reduction of energy dissipation compared to standard CMOS up to 200MHz. Energy saving by a typical factor of 10 can he achieved. The effect of supply voltage scaling is investigated as well as the sensitivity to technological parameters. It is shown that different effects due to inter-die and intra-die variations of the threshold voltage can strongly affect the performance of adiabatic circuits, increasing the energy dissipation by 7.7%.