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This article considers the experimental research of transient processes that occur in digital phase-locked loops (DPLL) after closing the feedback loop. Firmware implementation of DPLL device was made for this purpose. The paper shows the block diagram of the DPLL and describes its mathematical model. In particular, the location of poles and zeros of DPLL transfer function was determined by the transfer function of the 2nd order analog PLL and the formulas for digital filter coefficients were deducted. The article also represents the block diagram of hardware part of the firmware DPLL. Its key part is the STM microcontroller which is connected to the PC. For convenience reasons, the unique interface between the microcontroller and the PC was created in order to present waveforms of several signals simultaneously. Moreover, the paper depicts the algorithm of software part of the firmware DPLL in general as well as the detailed algorithm of voltage-controlled oscillator (VCO) operation – it works as direct digital synthesizer (DDS). The experimental research of the frequency acquisition process of harmonic oscillation was performed for three different sets of DPLL parameters. For each case the location of DPLL poles and zeros and plots of DPLL key signals (tracking error, current frequency and phase of output signal) were shown. Obtained diagrams demonstrate that a change of the DPLL natural frequency and damping factor influences on the transient process duration. Pictures signal waveforms from oscilloscope confirm these results. Furthermore, the results of the firmware DPLL research correspond to investigation results of existing simulation model of this DPLL with sufficient accuracy.

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