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We present a new low-noise, low-power SiGe transimpedance amplifier (TIA) by combining an automatic DC photo-current cancellation, an on-chip DC offset compensation circuit and a single-ended to differential conversion scheme. The conversion method is based of the replica biasing technique in order to provide balanced output signals to the subsequent stages. The chip was fabricated in a 0.18 μm SiGe BiCMOS technology. Experimental results show excellent performances such as 11 GHz bandwidth, 75-dBΩ transimpedance, -19.2 dBm sensitivity measured at 10 Gb/s at a Bit Error Rate (BER) of 10-12, [Formula: see text] input referred noise, and 9.5 ps peak-to-peak jitter which are the best overall performances reported in its category. The photoreceiver chip is expected to dissipate only 120 mW from a single 3.3 V power supply.

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We propose a Design for Stability (DFS) methodology dedicated to the design of reliable high-speed integrated photoreceiver front-ends. This methodology based on the stability factor, S-parameters and Z -parameters analysis is made of four rules that high-speed designers will apply during the stability check of their design. To demonstrate its effectiveness, the proposed DFS methodology was applied to build a transimpedance amplifier (TIA) compliant to Synchronous Optical Network (SONET) OC-192 (10-Gb/s) standard. Experimental results in agreement with initial design specifications show excellent performances such as: 11 GHz bandwidth, −20 dBm sensitivity measured at 10-Gb/s for a Bit Error Rate (BER) of 10 −9 and 10 ps peak-to-peak jitter.

Although emerginglightwave communication technologies are bringing 10 Gb/s systems into commercial use, optoelectronic inte~aces are stills limiting factors for better performances. In this papel; we address power penalty in high-speed burst-mode operation and, present a system-level noise analysis. The proposed architecture is insensitive to parasitic input loading this enable overcoming speed limitations at the receiver's input. A 2.7GHz bandwidth, a transimpedance of 47 dBR and an average input noise current density of 12 p A / m z have been achieved in simulations.