The corner effect is known as a leakage current enhancement at the edges of the active areas in the shallow trench isolated CMOS transistors. It usually deterio rates the transistor performance. In this work, the corner effect for FinFET tra nsistors with the minimum feature size of 50 nm is investigated by coupled three -dimensional process and device simulation. In contrast to earlier CMOS generati ons, the corner effect in small size FinFETs for typical device parameters does not lead to an additional leakage current and therefore does not deteriorate the FinFET transistor performance. This holds for both double and triple gate Fin FETs

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