In this paper a new failure technique for IGBT is presented, the method is based on analysis and measurement of gate voltage signal. The physical model equations and failure mechanisms of IGBT reported in the literature are used to define the failure detection criterion. Some experimental results of a gate voltage signal measurement in a fault free and faulty case is presented to validate proposed technique.

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This paper focuses on the comparative study of cascaded multilevel inverter whit two inverter cells, symmetric (5 levels) and asymmetrical (7 and 9 levels). These inverters are implemented without changes in the Power Semiconductor Devices, only modify the control stage and input supply voltages in the cells. This work presents the analysis of the output voltage total harmonic distortion (THD) and shows the results in simulation of cascaded multilevel inverters symmetrical and asymmetrical.

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